riscv: Weakly define invalidate_icache_range()

Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a
vendor-specific way to invalidate a portion of the instruction cache.
Allow them to override invalidate_icache_range().

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c
index c46b49eb0ac635b54be26938a23efe6e011b7aa2..afad7e117f32e8c03db8359ed2be131f14d163bd 100644 (file)
--- a/arch/riscv/lib/cache.c
+++ b/arch/riscv/lib/cache.c
@@ -19,7 +19,7 @@ __weak void flush_dcache_range(unsigned long start, unsigned long end)
 {
 }
 
-void invalidate_icache_range(unsigned long start, unsigned long end)
+__weak void invalidate_icache_range(unsigned long start, unsigned long end)
 {
        /*
         * RISC-V does not have an instruction for invalidating parts of the