clk: Add fixed-factor clock driver

This patch adds fixed-factor clock driver which derives clock
rate by dividing (div) and multiplying (mult) fixed factors
to a parent clock.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index d4c708c79e8bf4bef815911885da5e5e1bd8c4d2..87d8e5bcc98b4ac8e4cd774d60250e39f4c6b04c 100644 (file)
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -203,6 +203,14 @@
                        #clock-cells = <0>;
                        clock-frequency = <1234>;
                };
+
+               clk_fixed_factor: clk-fixed-factor {
+                       compatible = "fixed-factor-clock";
+                       #clock-cells = <0>;
+                       clock-div = <3>;
+                       clock-mult = <2>;
+                       clocks = <&clk_fixed>;
+               };
        };
 
        clk_sandbox: clk-sbox {

diff --git a/doc/device-tree-bindings/clock/fixed-factor-clock.txt b/doc/device-tree-bindings/clock/fixed-factor-clock.txt
new file mode 100644 (file)
index 0000000..1bae852
--- /dev/null
+++ b/doc/device-tree-bindings/clock/fixed-factor-clock.txt
@@ -0,0 +1,24 @@
+Binding for simple fixed factor rate clock sources.
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be "fixed-factor-clock".
+- #clock-cells : from common clock binding; shall be set to 0.
+- clock-div: fixed divider.
+- clock-mult: fixed multiplier.
+- clocks: parent clock.
+
+Optional properties:
+- clock-output-names : From common clock binding.
+
+Example:
+       clock {
+               compatible = "fixed-factor-clock";
+               clocks = <&parentclk>;
+               #clock-cells = <0>;
+               clock-div = <2>;
+               clock-mult = <1>;
+       };

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index de3d60ed05d21d6e151095f83e4c07d6e7f47259..1d9d725cae17a3ab79bea3115c5e61fbde64b65a 100644 (file)
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -4,7 +4,9 @@
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 
-obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o clk_fixed_rate.o
+obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o
+obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_rate.o
+obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_factor.o
 
 obj-y += imx/
 obj-y += tegra/

diff --git a/drivers/clk/clk_fixed_factor.c b/drivers/clk/clk_fixed_factor.c
new file mode 100644 (file)
index 0000000..5fa20a8
--- /dev/null
+++ b/drivers/clk/clk_fixed_factor.c
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ *
+ * Author: Anup Patel <anup.patel@wdc.com>
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <div64.h>
+#include <dm.h>
+
+struct clk_fixed_factor {
+       struct clk parent;
+       unsigned int div;
+       unsigned int mult;
+};
+
+#define to_clk_fixed_factor(dev)       \
+       ((struct clk_fixed_factor *)dev_get_platdata(dev))
+
+static ulong clk_fixed_factor_get_rate(struct clk *clk)
+{
+       uint64_t rate;
+       struct clk_fixed_factor *ff = to_clk_fixed_factor(clk->dev);
+
+       if (clk->id != 0)
+               return -EINVAL;
+
+       rate = clk_get_rate(&ff->parent);
+       if (IS_ERR_VALUE(rate))
+               return rate;
+
+       do_div(rate, ff->div);
+
+       return rate * ff->mult;
+}
+
+const struct clk_ops clk_fixed_factor_ops = {
+       .get_rate = clk_fixed_factor_get_rate,
+};
+
+static int clk_fixed_factor_ofdata_to_platdata(struct udevice *dev)
+{
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+       int err;
+       struct clk_fixed_factor *ff = to_clk_fixed_factor(dev);
+
+       err = clk_get_by_index(dev, 0, &ff->parent);
+       if (err)
+               return err;
+
+       ff->div = dev_read_u32_default(dev, "clock-div", 1);
+       ff->mult = dev_read_u32_default(dev, "clock-mult", 1);
+#endif
+
+       return 0;
+}
+
+static const struct udevice_id clk_fixed_factor_match[] = {
+       {
+               .compatible = "fixed-factor-clock",
+       },
+       { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(clk_fixed_factor) = {
+       .name = "fixed_factor_clock",
+       .id = UCLASS_CLK,
+       .of_match = clk_fixed_factor_match,
+       .ofdata_to_platdata = clk_fixed_factor_ofdata_to_platdata,
+       .platdata_auto_alloc_size = sizeof(struct clk_fixed_factor),
+       .ops = &clk_fixed_factor_ops,
+};

diff --git a/test/dm/clk.c b/test/dm/clk.c
index 898c034e27bfb1de7dc0b18f190f2dfb354714e4..112d5cbbc91c133ae4518b4881cd4731b2da0ced 100644 (file)
--- a/test/dm/clk.c
+++ b/test/dm/clk.c
@@ -12,12 +12,15 @@
 
 static int dm_test_clk(struct unit_test_state *uts)
 {
-       struct udevice *dev_fixed, *dev_clk, *dev_test;
+       struct udevice *dev_fixed, *dev_fixed_factor, *dev_clk, *dev_test;
        ulong rate;
 
        ut_assertok(uclass_get_device_by_name(UCLASS_CLK, "clk-fixed",
                                              &dev_fixed));
 
+       ut_assertok(uclass_get_device_by_name(UCLASS_CLK, "clk-fixed-factor",
+                                             &dev_fixed_factor));
+
        ut_assertok(uclass_get_device_by_name(UCLASS_CLK, "clk-sbox",
                                              &dev_clk));
        ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));