arm64: zynqmp: Add L2 cache nodes

Linux kernel throws "cacheinfo: Unable to detect cache hierarchy for
CPU 0" warning when booting on zu+ Soc. To fix it add the L2 cache
node and let each CPU point to it.

Reported-by: John Toomey <john.toomey@amd.com>
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c8dfabab12c97922aaad7fa91be0cbc7e4021528.1688992653.git.michal.simek@amd.com

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 38114d55386b01c96553d86bc0ee2b1b3358bed8..59b52919f130fde9ce475da87f37264425bad88f 100644 (file)
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -33,6 +33,7 @@
                        operating-points-v2 = <&cpu_opp_table>;
                        reg = <0x0>;
                        cpu-idle-states = <&CPU_SLEEP_0>;
+                       next-level-cache = <&L2>;
                };
 
                cpu1: cpu@1 {
@@ -42,6 +43,7 @@
                        reg = <0x1>;
                        operating-points-v2 = <&cpu_opp_table>;
                        cpu-idle-states = <&CPU_SLEEP_0>;
+                       next-level-cache = <&L2>;
                };
 
                cpu2: cpu@2 {
@@ -51,6 +53,7 @@
                        reg = <0x2>;
                        operating-points-v2 = <&cpu_opp_table>;
                        cpu-idle-states = <&CPU_SLEEP_0>;
+                       next-level-cache = <&L2>;
                };
 
                cpu3: cpu@3 {
@@ -60,6 +63,13 @@
                        reg = <0x3>;
                        operating-points-v2 = <&cpu_opp_table>;
                        cpu-idle-states = <&CPU_SLEEP_0>;
+                       next-level-cache = <&L2>;
+               };
+
+               L2: l2-cache {
+                       compatible = "cache";
+                       cache-level = <2>;
+                       cache-unified;
                };
 
                idle-states {