phy: atheros: Clarify the configuration of the CLK_25M output pin

Also take the opportunity to use the phy_read_mmd and phy_write_mmd
convenience functions.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index c0c2b4db3964a624c14d37f877bfc1982e7ff8f0..1da18eb5d45e57c40cf330082981199f3925e7f5 100644 (file)
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -17,6 +17,15 @@
 #define AR803x_DEBUG_REG_0             0x0
 #define AR803x_RGMII_RX_CLK_DLY                BIT(15)
 
+/* CLK_25M register is at MMD 7, address 0x8016 */
+#define AR803x_CLK_25M_SEL_REG         0x8016
+/* AR8035: Select frequency on CLK_25M pin through bits 4:3 */
+#define AR8035_CLK_25M_FREQ_25M                (0 | 0)
+#define AR8035_CLK_25M_FREQ_50M                (0 | BIT(3))
+#define AR8035_CLK_25M_FREQ_62M                (BIT(4) | 0)
+#define AR8035_CLK_25M_FREQ_125M       (BIT(4) | BIT(3))
+#define AR8035_CLK_25M_MASK            GENMASK(4, 3)
+
 static void ar803x_enable_rx_delay(struct phy_device *phydev, bool on)
 {
        int regval;
@@ -78,11 +87,11 @@ static int ar8035_config(struct phy_device *phydev)
 {
        int regval;
 
-       phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x0007);
-       phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
-       phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
-       regval = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
-       phy_write(phydev, MDIO_DEVAD_NONE, 0xe, (regval|0x0018));
+       /* Configure CLK_25M output clock at 125 MHz */
+       regval = phy_read_mmd(phydev, MDIO_MMD_AN, AR803x_CLK_25M_SEL_REG);
+       regval &= ~AR8035_CLK_25M_MASK; /* No surprises */
+       regval |= AR8035_CLK_25M_FREQ_125M;
+       phy_write_mmd(phydev, MDIO_MMD_AN, AR803x_CLK_25M_SEL_REG, regval);
 
        if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
            (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID))