riscv: remove dram_init_banksize()

Remove dram_init_banksize() on the architecture level.

Limiting used RAM to under 4 GiB is only necessary for CPUs which have a
DMA issue. SoC specific code already exists for FU540, FU740, JH7110.

Not all RISC-V boards will have memory below 4 GiB.

A weak implementation of dram_init_banksize() exists in common/board_f.c.

See the discussion in
https://lore.kernel.org/u-boot/545fe813-cb1e-469c-a131-0025c77aeaa2@canonical.com/T/

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

diff --git a/arch/riscv/cpu/generic/dram.c b/arch/riscv/cpu/generic/dram.c
index 94d8018407e6e94bcbc60b54e11a9c1be9dd29d4..1b51bae9b661d0c64fbcdde1ae4a2f72a2490abe 100644 (file)
--- a/arch/riscv/cpu/generic/dram.c
+++ b/arch/riscv/cpu/generic/dram.c
@@ -20,19 +20,3 @@ int dram_init_banksize(void)
 {
        return fdtdec_setup_memory_banksize();
 }
-
-phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
-{
-       /*
-        * Ensure that we run from first 4GB so that all
-        * addresses used by U-Boot are 32bit addresses.
-        *
-        * This in-turn ensures that 32bit DMA capable
-        * devices work fine because DMA mapping APIs will
-        * provide 32bit DMA addresses only.
-        */
-       if (gd->ram_top >= SZ_4G)
-               return SZ_4G - 1;
-
-       return gd->ram_top;
-}