/* dram_init must store complete ramsize in gd->ram_size */
gd->ram_size = get_ram_size(
(void *)CFG_SYS_SDRAM_BASE,
- CONFIG_MAX_RAM_BANK_SIZE);
+ CFG_MAX_RAM_BANK_SIZE);
return 0;
}
/* dram_init must store complete ramsize in gd->ram_size */
gd->ram_size = get_ram_size(
(void *)CFG_SYS_SDRAM_BASE,
- CONFIG_MAX_RAM_BANK_SIZE);
+ CFG_MAX_RAM_BANK_SIZE);
return 0;
}
/* dram_init must store complete ramsize in gd->ram_size */
gd->ram_size = get_ram_size(
(void *)CFG_SYS_SDRAM_BASE,
- CONFIG_MAX_RAM_BANK_SIZE);
+ CFG_MAX_RAM_BANK_SIZE);
}
#endif
omap_sdram_size()
#else
get_ram_size((void *)CFG_SYS_SDRAM_BASE,
- CONFIG_MAX_RAM_BANK_SIZE)
+ CFG_MAX_RAM_BANK_SIZE)
#endif
- sec_mem_size));
return sec_mem_start;
/* dram_init must store complete ramsize in gd->ram_size */
gd->ram_size = get_ram_size(
(long *) orion5x_sdram_bar(0),
- CONFIG_MAX_RAM_BANK_SIZE);
+ CFG_MAX_RAM_BANK_SIZE);
return 0;
}
gd->bd->bi_dram[i].start = orion5x_sdram_bar(i);
gd->bd->bi_dram[i].size = get_ram_size(
(long *) (gd->bd->bi_dram[i].start),
- CONFIG_MAX_RAM_BANK_SIZE);
+ CFG_MAX_RAM_BANK_SIZE);
}
return 0;
#define MVCPU_WIN_ENABLE ORION5X_WIN_ENABLE
#define MVCPU_WIN_DISABLE ORION5X_WIN_DISABLE
-#define CONFIG_MAX_RAM_BANK_SIZE (64*1024*1024)
+#define CFG_MAX_RAM_BANK_SIZE (64*1024*1024)
/* include here SoC variants. 5181, 5281, 6183 should go here when
adding support for them, and this comment should then be updated. */
/* Detect memory physically present */
gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
- CONFIG_MAX_RAM_BANK_SIZE);
+ CFG_MAX_RAM_BANK_SIZE);
/* Reconfigure memory for actual detected size */
switch (gd->ram_size) {
ddr3_size = ddr3_init();
gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE,
- CONFIG_MAX_RAM_BANK_SIZE);
+ CFG_MAX_RAM_BANK_SIZE);
#if defined(CONFIG_TI_AEMIF)
if (!(board_is_k2g_ice() || board_is_k2g_i1()))
aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
#ifndef __CONFIG_AM43XX_EVM_H
#define __CONFIG_AM43XX_EVM_H
-#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 21) /* 2GB */
+#define CFG_MAX_RAM_BANK_SIZE (1024 << 21) /* 2GB */
#define CFG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
#include <asm/arch/omap.h>
#endif /* CONFIG_DM */
-#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
+#define CFG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
/* Timer information */
#define CFG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
#ifndef __CONFIG_CM_T43_H
#define __CONFIG_CM_T43_H
-#define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2GB */
+#define CFG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2GB */
#define CFG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
#include <asm/arch/omap.h>
*/
#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
-#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
+#define CFG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
/* memtest start addr */
/* memtest will be run on 16MB */
"led1=64,0,1\0"
/* Physical Memory Map */
-#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
+#define CFG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
/* Default env settings */
#define CFG_EXTRA_ENV_SETTINGS \
"led5=63,0,1\0"
/* Physical Memory Map */
-#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
+#define CFG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
#define EEPROM_ADDR_DDR3 0x90
#define EEPROM_ADDR_CHIP 0x120
*/
#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
-#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
+#define CFG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
/* memtest start addr */
*/
#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
#define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */
-#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
+#define CFG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
/* memtest start addr */
"led0=117,0,1\0" \
/* Physical Memory Map */
-#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* 1GB */
+#define CFG_MAX_RAM_BANK_SIZE (512 << 20) /* 1GB */
/* Use common default */
"led5=63,0,1\0"
/* Physical Memory Map */
-#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
+#define CFG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
#define EEPROM_ADDR_DDR3 0x90
#define EEPROM_ADDR_CHIP 0x120
#define DDR_PLL_FREQ 303
/* Physical Memory Map */
-#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MiB */
+#define CFG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MiB */
/* Watchdog */
#define WATCHDOG_TRIGGER_GPIO 14
"led1=64,0,1\0"
/* Physical Memory Map */
-#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
+#define CFG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
#define EEPROM_ADDR_DDR3 0x90
#define EEPROM_ADDR_CHIP 0x120
#define V_OSCK 24000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
-#define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2048MB */
+#define CFG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2048MB */
#define CFG_SYS_SDRAM_BASE 0x80000000
/**
#ifndef __CONFIG_TI_AM335X_COMMON_H__
#define __CONFIG_TI_AM335X_COMMON_H__
-#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
+#define CFG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
#define CFG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
#include <asm/arch/omap.h>
/* Memory Configuration */
#define CFG_SYS_LPAE_SDRAM_BASE 0x800000000
-#define CONFIG_MAX_RAM_BANK_SIZE (2 << 30) /* 2GB */
+#define CFG_MAX_RAM_BANK_SIZE (2 << 30) /* 2GB */
#ifdef CONFIG_SYS_MALLOC_F_LEN
#define SPL_MALLOC_F_SIZE CONFIG_SYS_MALLOC_F_LEN
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