LIBS += $(CPUDIR)/$(SOC)/lib$(SOC).a
endif
ifeq ($(CPU),ixp)
-LIBS += cpu/ixp/npe/libnpe.a
+LIBS += arch/arm/cpu/ixp/npe/libnpe.a
endif
LIBS += arch/$(ARCH)/lib/lib$(ARCH).a
LIBS += fs/cramfs/libcramfs.a fs/fat/libfat.a fs/fdos/libfdos.a fs/jffs2/libjffs2.a \
. = ALIGN(4);
.text :
{
- cpu/arm1136/start.o (.text)
+ arch/arm/cpu/arm1136/start.o (.text)
*(.text)
}
. = ALIGN(4);
.text :
{
- cpu/arm1176/start.o (.text)
+ arch/arm/cpu/arm1176/start.o (.text)
*(.text)
}
. = ALIGN(4);
.text :
{
- cpu/arm720t/start.o (.text)
+ arch/arm/cpu/arm720t/start.o (.text)
*(.text)
}
. = ALIGN(4);
.text :
{
- cpu/arm920t/start.o (.text)
+ arch/arm/cpu/arm920t/start.o (.text)
/* the EP93xx expects to find the pattern 'CRUS' at 0x1000 */
. = 0x1000;
LONG(0x53555243)
. = ALIGN(4);
.text :
{
- cpu/arm920t/start.o (.text)
+ arch/arm/cpu/arm920t/start.o (.text)
*(.text)
}
. = ALIGN(4);
.text :
{
- cpu/arm925t/start.o (.text)
+ arch/arm/cpu/arm925t/start.o (.text)
*(.text)
}
MX27OBJS = reset.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-SRCS += $(addprefix $(SRCTREE)/cpu/arm926ejs/mx27/,$(MX27OBJS:.o=.c))
+SRCS += $(addprefix $(SRCTREE)/arch/arm/cpu/arm926ejs/mx27/,$(MX27OBJS:.o=.c))
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS) $(MX27OBJS))
all: $(obj).depend $(LIB)
. = ALIGN(4);
.text :
{
- cpu/arm926ejs/start.o (.text)
+ arch/arm/cpu/arm926ejs/start.o (.text)
*(.text)
}
. = ALIGN(4);
.text :
{
- cpu/arm946es/start.o (.text)
+ arch/arm/cpu/arm946es/start.o (.text)
*(.text)
}
. = ALIGN(4);
.text :
{
- cpu/arm_cortexa8/start.o
+ arch/arm/cpu/arm_cortexa8/start.o
*(.text)
}
* Copyright (C) 2009 Samsung Electronics
* Minkyu Kang <mk7.kang@samsung.com>
*
- * based on cpu/arm_cortexa8/omap3/cache.S
+ * based on arch/arm/cpu/arm_cortexa8/omap3/cache.S
*
* See file CREDITS for list of people who contributed to this
* project.
. = ALIGN(4);
.text :
{
- cpu/arm_cortexa8/start.o (.text)
+ arch/arm/cpu/arm_cortexa8/start.o (.text)
*(.text)
}
. = ALIGN(4);
.text :
{
- cpu/arm_intcm/start.o (.text)
+ arch/arm/cpu/arm_intcm/start.o (.text)
*(.text)
}
LIB := $(obj)libnpe.a
-LOCAL_CFLAGS += -I$(TOPDIR)/cpu/ixp/npe/include -DCONFIG_IXP425_COMPONENT_ETHDB -D__linux
+LOCAL_CFLAGS += -I$(TOPDIR)/arch/arm/cpu/ixp/npe/include -DCONFIG_IXP425_COMPONENT_ETHDB -D__linux
CFLAGS += $(LOCAL_CFLAGS)
HOSTCFLAGS += $(LOCAL_CFLAGS)
. = ALIGN(4);
.text :
{
- cpu/ixp/start.o(.text)
+ arch/arm/cpu/ixp/start.o(.text)
*(.text)
}
. = ALIGN(4);
.text :
{
- cpu/lh7a40x/start.o (.text)
+ arch/arm/cpu/lh7a40x/start.o (.text)
*(.text)
}
. = ALIGN(4);
.text :
{
- cpu/pxa/start.o (.text)
+ arch/arm/cpu/pxa/start.o (.text)
*(.text)
}
. = ALIGN(4);
.text :
{
- cpu/s3c44b0/start.o (.text)
+ arch/arm/cpu/s3c44b0/start.o (.text)
*(.text)
}
. = ALIGN(4);
.text :
{
- cpu/sa1100/start.o (.text)
+ arch/arm/cpu/sa1100/start.o (.text)
*(.text)
}
/*
- * needed for cpu/arm_cortexa8/mx51/lowlevel_init.S
+ * needed for arch/arm/cpu/arm_cortexa8/mx51/lowlevel_init.S
*
* These should be auto-generated
*/
TEXT_BASE = 0x00e00000
# include NPE ethernet driver
-BOARDLIBS = cpu/ixp/npe/libnpe.a
+BOARDLIBS = arch/arm/cpu/ixp/npe/libnpe.a
LDSCRIPT := $(SRCTREE)/board/$(BOARDDIR)/u-boot.lds
. = ALIGN (4);
.text : {
- cpu/ixp/start.o(.text)
+ arch/arm/cpu/ixp/start.o(.text)
lib/string.o(.text)
lib/vsprintf.o(.text)
arch/arm/lib/board.o(.text)
common/dlmalloc.o(.text)
- cpu/ixp/cpu.o(.text)
+ arch/arm/cpu/ixp/cpu.o(.text)
. = env_offset;
common/env_embedded.o(.ppcenv)
* (.text)
TEXT_BASE = 0x00e00000
# include NPE ethernet driver
-BOARDLIBS = cpu/ixp/npe/libnpe.a
+BOARDLIBS = arch/arm/cpu/ixp/npe/libnpe.a
LDSCRIPT := $(SRCTREE)/board/$(BOARDDIR)/u-boot.lds
. = ALIGN (4);
.text : {
- cpu/ixp/start.o(.text)
+ arch/arm/cpu/ixp/start.o(.text)
lib/string.o(.text)
lib/vsprintf.o(.text)
arch/arm/lib/board.o(.text)
common/dlmalloc.o(.text)
- cpu/ixp/cpu.o(.text)
+ arch/arm/cpu/ixp/cpu.o(.text)
. = env_offset;
common/env_embedded.o (.ppcenv)
TEXT_BASE = 0x00e00000
# include NPE ethernet driver
-BOARDLIBS = cpu/ixp/npe/libnpe.a
+BOARDLIBS = arch/arm/cpu/ixp/npe/libnpe.a
LDSCRIPT := $(SRCTREE)/board/$(BOARDDIR)/u-boot.lds
. = ALIGN (4);
.text : {
- cpu/ixp/start.o (.text)
+ arch/arm/cpu/ixp/start.o (.text)
lib/string.o (.text)
lib/vsprintf.o (.text)
arch/arm/lib/board.o (.text)
common/dlmalloc.o (.text)
- cpu/ixp/cpu.o (.text)
+ arch/arm/cpu/ixp/cpu.o (.text)
. = env_offset;
common/env_embedded.o (.ppcenv)
TEXT_BASE = 0x00e00000
# include NPE ethernet driver
-BOARDLIBS = cpu/ixp/npe/libnpe.a
+BOARDLIBS = arch/arm/cpu/ixp/npe/libnpe.a
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
* Board-specific low level initialization code. Called at the very end
- * of cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no
+ * of arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no
* initialization required.
*
* This program is free software; you can redistribute it and/or
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
* Board-specific low level initialization code. Called at the very end
- * of cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no
+ * of arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no
* initialization required.
*
* This program is free software; you can redistribute it and/or
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
* Board-specific low level initialization code. Called at the very end
- * of cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no
+ * of arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no
* initialization required.
*
* This program is free software; you can redistribute it and/or
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
* Board-specific low level initialization code. Called at the very end
- * of cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no
+ * of arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no
* initialization required.
*
* For _OLDER_ Sonata boards sets up GPIO4 to control NAND WP line. Newer
-LDSCRIPT := $(SRCTREE)/cpu/arm920t/ep93xx/u-boot.lds
+LDSCRIPT := $(SRCTREE)/arch/arm/cpu/arm920t/ep93xx/u-boot.lds
ifdef CONFIG_EDB9301
TEXT_BASE = 0x05700000
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/arm1136/start.o (.text)
+ arch/arm/cpu/arm1136/start.o (.text)
board/freescale/mx31ads/libmx31ads.a (.text)
arch/arm/lib/libarm.a (.text)
net/libnet.a (.text)
/*
* This the the zoom2, board specific, gpmc configuration for the
* quad uart on the debug board. The more general gpmc configurations
- * are setup at the cpu level in cpu/arm_cortexa8/omap3/mem.c
+ * are setup at the cpu level in arch/arm/cpu/arm_cortexa8/omap3/mem.c
*
* The details of the setting of the serial gpmc setup are not available.
* The values were provided by another party.
/*
* (C) Copyright 2006 Embedded Artists AB <www.embeddedartists.com>
*
- * Modified to use the routines in cpu/arm720t/lpc2292/flash.c by
+ * Modified to use the routines in arch/arm/cpu/arm720t/lpc2292/flash.c by
* Gary Jennejohn <garyj@denx,de>
*
* This program is free software; you can redistribute it and/or
. = ALIGN(4);
.text :
{
- cpu/arm1176/start.o (.text)
- cpu/arm1176/s3c64xx/cpu_init.o (.text)
+ arch/arm/cpu/arm1176/start.o (.text)
+ arch/arm/cpu/arm1176/s3c64xx/cpu_init.o (.text)
*(.text)
}
* (C) Copyright 2006 Embedded Artists AB <www.embeddedartists.com>
*
* (C) Copyright 2007 Gary Jennejohn garyj@denx.de
- * Modified to use the routines in cpu/arm720t/lpc2292/flash.c.
+ * Modified to use the routines in arch/arm/cpu/arm720t/lpc2292/flash.c.
* Heavily modified to support the SMN42 board from Siemens
*
* This program is free software; you can redistribute it and/or
* (C) Copyright 2003
* Martin Krause, TQ-Systems GmbH, <martin.krause@tqs.de>
*
- * Based on cpu/arm920t/serial.c, by Gary Jennejohn
+ * Based on arch/arm/cpu/arm920t/serial.c, by Gary Jennejohn
* (C) Copyright 2002 Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
*
* This program is free software; you can redistribute it and/or modify
* (C) Copyright 2003
* Martin Krause, TQ-Systems GmbH, <martin.krause@tqs.de>
*
- * Based on cpu/arm920t/serial.c, by Gary Jennejohn
+ * Based on arch/arm/cpu/arm920t/serial.c, by Gary Jennejohn
* (C) Copyright 2002 Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
*
* This program is free software; you can redistribute it and/or modify
. = ALIGN(4);
.text :
{
- cpu/arm920t/start.o (.text)
+ arch/arm/cpu/arm920t/start.o (.text)
lib/zlib.o (.text)
lib/crc32.o (.text)
lib/string.o (.text)
However, to avoid duplicating code through all processor files, a generic core
for ARM Integrator CMs has been added
- cpu/arm_intcm
+ arch/arm/cpu/arm_intcm
Otherwise. for example, the standard CM reset via the CM control register would
need placing in each CM processor file......
[By Steven Scholz <steven.scholz@imc-berlin.de>, 16 Aug 2004]
Since the cpu/ directory gets clobbered with peripheral driver code I
-started cleaning up cpu/arm920t.
+started cleaning up arch/arm/cpu/arm920t.
I introduced the concept of Soc (system on a chip) into the ./cpu
directory. That means that code that is cpu (i.e. core) specific
Thus a library/archive "$(CPUDIR)/$(SOC)/lib$(SOC).a" will be build
and linked. Examples will be
- cpu/arm920t/imx/
- cpu/arm920t/s3c24x0
+ arch/arm/cpu/arm920t/imx/
+ arch/arm/cpu/arm920t/s3c24x0
One can select an SoC by passing the name of it to ./mkconfig just
like
Files:
-cpu/arm720t/serial_netarm.c .. serial I/O for the cpu
+arch/arm/cpu/arm720t/serial_netarm.c .. serial I/O for the cpu
board/modnet50/lowlevel_init.S .. memory setup for ModNET50
board/modnet50/flash.c .. flash routines
COBJS = nand_boot_fsl_nfc.o
SRCS := $(SRCTREE)/nand_spl/nand_boot_fsl_nfc.c
-SRCS += $(SRCTREE)/cpu/arm1136/start.S
+SRCS += $(SRCTREE)/arch/arm/cpu/arm1136/start.S
SRCS += $(SRCTREE)/board/freescale/mx31pdk/lowlevel_init.S
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
__OBJS := $(SOBJS) $(COBJS)
#########################################################################
-$(obj)%.o: $(SRCTREE)/cpu/arm1136/%.S
+$(obj)%.o: $(SRCTREE)/arch/arm/cpu/arm1136/%.S
$(CC) $(AFLAGS) -c -o $@ $<
$(obj)%.o: $(SRCTREE)/board/freescale/mx31pdk/%.S
COBJS = nand_boot_fsl_nfc.o
SRCS := $(SRCTREE)/nand_spl/nand_boot_fsl_nfc.c
-SRCS += $(SRCTREE)/cpu/arm926ejs/start.S
+SRCS += $(SRCTREE)/arch/arm/cpu/arm926ejs/start.S
SRCS += $(SRCTREE)/board/karo/tx25/lowlevel_init.S
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
__OBJS := $(SOBJS) $(COBJS)
#########################################################################
-$(obj)%.o: $(SRCTREE)/cpu/arm926ejs/%.S
+$(obj)%.o: $(SRCTREE)/arch/arm/cpu/arm926ejs/%.S
$(CC) $(AFLAGS) -c -o $@ $<
$(obj)%.o: $(SRCTREE)/board/karo/tx25/%.S
# from cpu directory
$(obj)start.S:
@rm -f $@
- @ln -s $(TOPDIR)/cpu/arm1176/start.S $@
+ @ln -s $(TOPDIR)/arch/arm/cpu/arm1176/start.S $@
# from SoC directory
$(obj)cpu_init.S:
@rm -f $@
- @ln -s $(TOPDIR)/cpu/arm1176/s3c64xx/cpu_init.S $@
+ @ln -s $(TOPDIR)/arch/arm/cpu/arm1176/s3c64xx/cpu_init.S $@
# from board directory
$(obj)lowlevel_init.S: