arm64: zynqmp: zynqmp-zcu106-rev1.0: Fix DP PLL configuration

This patch fixes the DP audio and video PLL configurations for the zynqmp-zcu106-rev1.0 evaluation board.

The Linux DP driver expects the DP to be using the following PLL config:
  - DP video PLL should use the VPLL (0x0)
  - DP audio PLL should use the RPLL (0x3)

Register 0xFD1A0070 configures the DP video PLL.
Register 0xFD1A0074 configures the DP audio PLL.

Signed-off-by: Neal Frager <neal.frager@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/ae42ad6185418713a473660c8d15903299af7764.1652192319.git.michal.simek@amd.com

diff --git a/board/xilinx/zynqmp/zynqmp-zcu106-rev1.0/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu106-rev1.0/psu_init_gpl.c
index 2ac4e035d88707b9e00aa5c09ce57c7d7d328ae9..3dc9bf8f3a83c2f1367da7c1ba6c2895fba95abc 100644 (file)
--- a/board/xilinx/zynqmp/zynqmp-zcu106-rev1.0/psu_init_gpl.c
+++ b/board/xilinx/zynqmp/zynqmp-zcu106-rev1.0/psu_init_gpl.c
@@ -81,8 +81,8 @@ static unsigned long psu_clock_init_data(void)
        psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
        psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
        psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U);
-       psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010203U);
-       psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01013C00U);
+       psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010500U);
+       psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01013C03U);
        psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01011303U);
        psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
        psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);