/**
* Locations of the boot-device identifier in SRAM
*/
-#define BROM_BOOTSOURCE_ID_ADDR (CONFIG_IRAM_BASE + 0x10)
+#define BROM_BOOTSOURCE_ID_ADDR (CFG_IRAM_BASE + 0x10)
#endif
#include "rockchip-common.h"
/* FIXME: ff020000 is pmu_mem (10k), while ff0e0000 is regular int_mem */
-#define CONFIG_IRAM_BASE 0xff020000
+#define CFG_IRAM_BASE 0xff020000
#define GICD_BASE 0xff131000
#define GICC_BASE 0xff132000
#include <asm/arch-rockchip/hardware.h>
#include "rockchip-common.h"
-#define CONFIG_IRAM_BASE 0x10080000
+#define CFG_IRAM_BASE 0x10080000
#define CFG_SYS_SDRAM_BASE 0x60000000
#define SDRAM_BANK_SIZE (1024UL << 20UL)
#define CFG_SYS_HZ_CLOCK 24000000
-#define CONFIG_IRAM_BASE 0x10080000
+#define CFG_IRAM_BASE 0x10080000
/* RAW SD card / eMMC locations. */
#include <asm/arch-rockchip/hardware.h>
#include "rockchip-common.h"
-#define CONFIG_IRAM_BASE 0x10080000
+#define CFG_IRAM_BASE 0x10080000
/* spl size 32kb sram - 2kb bootrom */
#define CFG_SYS_HZ_CLOCK 24000000
-#define CONFIG_IRAM_BASE 0x10080000
+#define CFG_IRAM_BASE 0x10080000
#define CFG_SYS_SDRAM_BASE 0x60000000
#define SDRAM_BANK_SIZE (512UL << 20UL)
#define CFG_SYS_HZ_CLOCK 24000000
-#define CONFIG_IRAM_BASE 0xff700000
+#define CFG_IRAM_BASE 0xff700000
/* RAW SD card / eMMC locations. */
#include "rockchip-common.h"
-#define CONFIG_IRAM_BASE 0xfff80000
+#define CFG_IRAM_BASE 0xfff80000
#define CFG_SYS_SDRAM_BASE 0
#define SDRAM_MAX_SIZE 0xff000000
#include "rockchip-common.h"
-#define CONFIG_IRAM_BASE 0xff090000
+#define CFG_IRAM_BASE 0xff090000
/* FAT sd card locations. */
#define CFG_SYS_SDRAM_BASE 0
#define CFG_SYS_SDRAM_BASE 0
#define SDRAM_MAX_SIZE 0xff000000
-#define CONFIG_IRAM_BASE 0xff8c0000
+#define CFG_IRAM_BASE 0xff8c0000
#define ENV_MEM_LAYOUT_SETTINGS \
"scriptaddr=0x00500000\0" \
#include "rockchip-common.h"
-#define CONFIG_IRAM_BASE 0xff8c0000
+#define CFG_IRAM_BASE 0xff8c0000
/* FAT sd card locations. */
#define CFG_SYS_SDRAM_BASE 0
#include "rockchip-common.h"
-#define CONFIG_IRAM_BASE 0xfdcc0000
+#define CFG_IRAM_BASE 0xfdcc0000
#define CFG_SYS_SDRAM_BASE 0
#define SDRAM_MAX_SIZE 0xf0000000
#include <asm/arch-rockchip/hardware.h>
#include "rockchip-common.h"
-#define CONFIG_IRAM_BASE 0x10080000
+#define CFG_IRAM_BASE 0x10080000
#define CFG_SYS_TIMER_RATE (24 * 1000 * 1000)
/* TIMER1,initialized by ddr initialize code */