if (busno == pcie->first_busno && (dev != 0 || func != 0))
return false;
+ /* Access to other buses is possible when link is up */
+ if (busno != pcie->first_busno && !mvebu_pcie_link_up(pcie))
+ return false;
+
/* On secondary bus can be only one PCIe device */
if (busno == pcie->sec_busno && dev != 0)
return false;
struct pci_controller *hose = dev_get_uclass_priv(ctlr);
u32 reg;
- debug("%s: PCIe %d.%d - up, base %08x\n", __func__,
- pcie->port, pcie->lane, (u32)pcie->base);
-
/*
* Change Class Code of PCI Bridge device to PCI Bridge (0x600400)
* because default value is Memory controller (0x508000) which
if (ret < 0)
goto err;
- /* Check link and skip ports that have no link */
- if (!mvebu_pcie_link_up(pcie)) {
- debug("%s: %s - down\n", __func__, pcie->name);
- ret = -ENODEV;
- goto err;
- }
-
return 0;
err: