net: mvpp2x: Set BM pool high address

MVPP22 driver support 64 Bit arch and require BM pool
high address configuration.

Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 3fca987c2943129757d937f82fc89a8408097702..37056c2b637f329513f034c1af7235bc76bd259e 100644 (file)
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -316,6 +316,8 @@ do {                                                                        \
 #define            MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK   0xff00
 #define     MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT 8
 #define MVPP22_BM_MC_RLS_REG                   0x64d4
+#define MVPP22_BM_POOL_BASE_HIGH_REG           0x6310
+#define MVPP22_BM_POOL_BASE_HIGH_MASK          0xff
 
 /* TX Scheduler registers */
 #define MVPP2_TXP_SCHED_PORT_INDEX_REG         0x8000
@@ -2594,6 +2596,10 @@ static int mvpp2_bm_pool_create(struct udevice *dev,
 
        mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id),
                    lower_32_bits(bm_pool->dma_addr));
+       if (priv->hw_version == MVPP22)
+               mvpp2_write(priv, MVPP22_BM_POOL_BASE_HIGH_REG,
+                           (upper_32_bits(bm_pool->dma_addr) &
+                           MVPP22_BM_POOL_BASE_HIGH_MASK));
        mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size);
 
        val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));