]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
arm64: zynqmp: Set qspi tx-buswidth to 4
authorAmit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>
Tue, 10 May 2022 14:33:01 +0000 (16:33 +0200)
committerMichal Simek <michal.simek@amd.com>
Wed, 18 May 2022 11:17:18 +0000 (13:17 +0200)
In all the ZynqMP boards dts files tx-buswidth is by default set to 1. Due
to this the framework only issues 1-1-1 write commands to the GQSPI driver.
But the GQSPI controller is capable of handling 1-4-4 write commands, so
updated the tx-buswidth to 4 in ZynqMP boards dts files. This would enable
the spi-nor framework to issue 1-4-4 write commands instead of 1-1-1. This
will increase the tx data transfer rate, as now the tx data will be
transferred on four lines instead on single line.

Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/ad61199f55e5e00f29de6206d9d1872a52a7657e.1652193179.git.michal.simek@amd.com
18 files changed:
arch/arm/dts/zynqmp-m-a2197-01-revA.dts
arch/arm/dts/zynqmp-m-a2197-02-revA.dts
arch/arm/dts/zynqmp-m-a2197-03-revA.dts
arch/arm/dts/zynqmp-mini-qspi.dts
arch/arm/dts/zynqmp-sm-k26-revA.dts
arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts
arch/arm/dts/zynqmp-zc1232-revA.dts
arch/arm/dts/zynqmp-zc1254-revA.dts
arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
arch/arm/dts/zynqmp-zcu102-revA.dts
arch/arm/dts/zynqmp-zcu104-revA.dts
arch/arm/dts/zynqmp-zcu104-revC.dts
arch/arm/dts/zynqmp-zcu106-revA.dts
arch/arm/dts/zynqmp-zcu111-revA.dts
arch/arm/dts/zynqmp-zcu1275-revA.dts
arch/arm/dts/zynqmp-zcu208-revA.dts
arch/arm/dts/zynqmp-zcu216-revA.dts

index 86f2ccf4d95121336807f848c3d088d732bab6d2..7b3722f0808b21caa94a87394e7eeb90b2fe5051 100644 (file)
@@ -77,7 +77,7 @@
                #address-cells = <1>;
                #size-cells = <1>;
                reg = <0x0>;
-               spi-tx-bus-width = <1>;
+               spi-tx-bus-width = <4>;
                spi-rx-bus-width = <4>;
                spi-max-frequency = <108000000>;
        };
index e980fb07fc308a60d614b50d056826245df2356c..11b2a58a0f060d56d18d2528c17957182a068aa4 100644 (file)
@@ -73,7 +73,7 @@
                #address-cells = <1>;
                #size-cells = <1>;
                reg = <0x0>;
-               spi-tx-bus-width = <1>;
+               spi-tx-bus-width = <4>;
                spi-rx-bus-width = <4>;
                spi-max-frequency = <108000000>;
        };
index c8c5100672fe5d2e33a1f90634f780f5d75bb896..db199c467b0d5f27407e397f711cb2da9d91cb8a 100644 (file)
@@ -73,7 +73,7 @@
                #address-cells = <1>;
                #size-cells = <1>;
                reg = <0x0>;
-               spi-tx-bus-width = <1>;
+               spi-tx-bus-width = <4>;
                spi-rx-bus-width = <4>;
                spi-max-frequency = <108000000>;
        };
index 9b4320fe6e206a5b90aed4831b64f50944ebb312..20c21deb6673f03d64974e89ab59d73785196cd4 100644 (file)
@@ -68,7 +68,7 @@
                #address-cells = <1>;
                #size-cells = <1>;
                reg = <0x0>;
-               spi-tx-bus-width = <1>;
+               spi-tx-bus-width = <4>;
                spi-rx-bus-width = <4>;
                spi-max-frequency = <40000000>;
        };
index 14ab31685dfeceb2c3ed3d3bb91c74d8e7392c71..e904cd8ea093bba9a514caa5f410a3ba90b7003e 100644 (file)
                #address-cells = <1>;
                #size-cells = <1>;
                reg = <0>;
-               spi-tx-bus-width = <1>;
+               spi-tx-bus-width = <4>;
                spi-rx-bus-width = <4>;
                spi-max-frequency = <40000000>; /* 40MHz */
                partition@0 {
index 300e2ebe96e8dba526dcb6b336060edc7252a78e..3750bb38b585c7b6696932e6651de53b9cb0c40a 100644 (file)
@@ -61,7 +61,7 @@
                compatible = "st,m25p80", "n25q256a", "jedec,spi-nor";
                m25p,fast-read;
                reg = <0x0>;
-               spi-tx-bus-width = <1>;
+               spi-tx-bus-width = <4>;
                spi-rx-bus-width = <4>;
                spi-max-frequency = <166000000>;
                #address-cells = <1>;
index 7543855c9fda4f24df18ba30eeb8623728d4a00a..63c553f772425add261c86a8a7bbe5b1fbdb7ce7 100644 (file)
@@ -44,7 +44,7 @@
                #address-cells = <1>;
                #size-cells = <1>;
                reg = <0x0>;
-               spi-tx-bus-width = <1>;
+               spi-tx-bus-width = <4>;
                spi-rx-bus-width = <4>;
                spi-max-frequency = <108000000>; /* Based on DC1 spec */
                partition@0 { /* for testing purpose */
index 9cc1c0c6c5a7195fd57a5cb4f5a782d3205279d8..343033cc7e88d494950ff89482956ce25f915857 100644 (file)
@@ -45,7 +45,7 @@
                #address-cells = <1>;
                #size-cells = <1>;
                reg = <0x0>;
-               spi-tx-bus-width = <1>;
+               spi-tx-bus-width = <4>;
                spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
                spi-max-frequency = <108000000>; /* Based on DC1 spec */
                partition@0 { /* for testing purpose */
index 4a87bd6a6aafba5acddbc200165c721f57edf203..d20f6675687bfc366a3d0f5b40d3f1edd8d3f9ee 100644 (file)
                #address-cells = <1>;
                #size-cells = <1>;
                reg = <0x0>;
-               spi-tx-bus-width = <1>;
+               spi-tx-bus-width = <4>;
                spi-rx-bus-width = <4>;
                spi-max-frequency = <108000000>; /* Based on DC1 spec */
                partition@0 { /* for testing purpose */
index f420f83ad208f65e9f1a296beca899ea6385a1a5..e153a64f4fb609c2788cd2347575d6b95b7f56d8 100644 (file)
                #address-cells = <1>;
                #size-cells = <1>;
                reg = <0x0>;
-               spi-tx-bus-width = <1>;
+               spi-tx-bus-width = <4>;
                spi-rx-bus-width = <4>; /* also DUAL configuration possible */
                spi-max-frequency = <108000000>; /* Based on DC1 spec */
                partition@0 { /* for testing purpose */
index 1b1cabb004ff3e2ca23e2fbb5b995c5f046a9e9a..aac798d6e74ae35342b352c78cbde6d1f65f47e0 100644 (file)
                #address-cells = <1>;
                #size-cells = <1>;
                reg = <0x0>;
-               spi-tx-bus-width = <1>;
+               spi-tx-bus-width = <4>;
                spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
                spi-max-frequency = <108000000>; /* Based on DC1 spec */
                partition@0 { /* for testing purpose */
index 9cd30447eb3ed908e8920c7a5b20255f8bbf31f7..50bf479089135afa0a00bf5fd4d0d4b78b65ff6f 100644 (file)
                #address-cells = <1>;
                #size-cells = <1>;
                reg = <0x0>;
-               spi-tx-bus-width = <1>;
+               spi-tx-bus-width = <4>;
                spi-rx-bus-width = <4>;
                spi-max-frequency = <108000000>; /* Based on DC1 spec */
                partition@0 { /* for testing purpose */
index 45191569c101f10f818b142d23521da0b9411de7..752a9e38f3d34845432059256b778bcdb7a36c6b 100644 (file)
                #address-cells = <1>;
                #size-cells = <1>;
                reg = <0x0>;
-               spi-tx-bus-width = <1>;
+               spi-tx-bus-width = <4>;
                spi-rx-bus-width = <4>;
                spi-max-frequency = <108000000>; /* Based on DC1 spec */
                partition@0 { /* for testing purpose */
index 50cc72eb9240e92615db59ac6dfae4f3f04aa3ff..03624648cd7135618350eed8552039923c943a55 100644 (file)
                #address-cells = <1>;
                #size-cells = <1>;
                reg = <0x0>;
-               spi-tx-bus-width = <1>;
+               spi-tx-bus-width = <4>;
                spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
                spi-max-frequency = <108000000>; /* Based on DC1 spec */
                partition@0 { /* for testing purpose */
index 2b15ce1ea8471495eb79638caf223b41e7b12eb8..021fe88670fb8af4f05da562a1e5b02c414f8efe 100644 (file)
                #address-cells = <1>;
                #size-cells = <1>;
                reg = <0x0>;
-               spi-tx-bus-width = <1>;
+               spi-tx-bus-width = <4>;
                spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
                spi-max-frequency = <108000000>; /* Based on DC1 spec */
                partition@0 { /* for testing purpose */
index 10d8bc8f9a19fbc0508dcaf873c6546a7aca5af7..e88fc23b1f1454537d6afd7e6cde3884de208a4d 100644 (file)
@@ -50,7 +50,7 @@
                #address-cells = <1>;
                #size-cells = <1>;
                reg = <0x0>;
-               spi-tx-bus-width = <1>;
+               spi-tx-bus-width = <4>;
                spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
                spi-max-frequency = <108000000>; /* Based on DC1 spec */
                partition@0 { /* for testing purpose */
index 32a6e6fb55e2fe7c8d967827406427410bf88e37..c5cdd58af6edddbbf785144e0e621e962241f2ae 100644 (file)
                #address-cells = <1>;
                #size-cells = <1>;
                reg = <0>;
-               spi-tx-bus-width = <1>;
+               spi-tx-bus-width = <4>;
                spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
                spi-max-frequency = <108000000>; /* Based on DC1 spec */
        };
index 1e347036d0a7bb08643d3bd75da70679a2c148c5..caae16965d6f8419dd8cba51e4e583121bc56924 100644 (file)
                #address-cells = <1>;
                #size-cells = <1>;
                reg = <0x0>;
-               spi-tx-bus-width = <1>;
+               spi-tx-bus-width = <4>;
                spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
                spi-max-frequency = <108000000>; /* Based on DC1 spec */
        };