Switch PHY_ANEG_TIMEOUT to CONFIG_PHY_ANEG_TIMEOUT Kconfig symbol.
This removes one more configuration headers option finalizes its
Kconfig symbol conversion. No functional change expected.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x180000
CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_GIGE=y
CONFIG_MII=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_MII=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_POWER_TPS65218=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x180000
CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_GIGE=y
CONFIG_MII=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x180000
CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_GIGE=y
CONFIG_MII=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x180000
CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_GIGE=y
CONFIG_MII=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_MII=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_POWER_TPS65218=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_MII=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_MII=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_MII=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
+CONFIG_PHY_ANEG_TIMEOUT=15000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_FEC_MXC=y
CONFIG_SF_DEFAULT_BUS=1
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y
CONFIG_SF_DEFAULT_BUS=1
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y
CONFIG_SF_DEFAULT_BUS=1
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
+CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_MVPP2=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y
CONFIG_MMC_SDHCI_MV=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ANEG_TIMEOUT=16000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y
CONFIG_SF_DEFAULT_BUS=1
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_REALTEK=y
CONFIG_RENESAS_RAVB=y
CONFIG_DM_REGULATOR=y
CONFIG_LED_GPIO=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_MSM=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_PHY_FIXED=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHYLIB=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_DM_MDIO=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DWC_ETH_QOS=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH_PHY=y
# CONFIG_SPI_FLASH_UNLOCK_ALL is not set
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_MICREL=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH_PHY=y
CONFIG_PHY_GIGE=y
# CONFIG_SPI_FLASH_UNLOCK_ALL is not set
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_PHY_SMSC=y
# CONFIG_SPI_FLASH_UNLOCK_ALL is not set
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_PHY_SMSC=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH_PHY=y
CONFIG_PHY_GIGE=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH_PHY=y
CONFIG_PHY_GIGE=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH_PHY=y
CONFIG_PHY_GIGE=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_PHYLIB=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_FEC_MXC=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH_PHY=y
CONFIG_PHY_GIGE=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH_PHY=y
CONFIG_PHY_GIGE=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_ADIN=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_REALTEK=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
+CONFIG_PHY_ANEG_TIMEOUT=10000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
+CONFIG_PHY_ANEG_TIMEOUT=10000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_TI=y
CONFIG_PHY_GIGE=y
CONFIG_FEC_MXC=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MSCC=y
CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_TI=y
CONFIG_DM_ETH_PHY=y
CONFIG_PHY_GIGE=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
+CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MARVELL=y
CONFIG_DM_MDIO=y
CONFIG_DM_ETH_PHY=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH_PHY=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH_PHY=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH_PHY=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH_PHY=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH_PHY=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH_PHY=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH_PHY=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHYLIB_10G=y
CONFIG_PHY_MARVELL_10G=y
CONFIG_DM_ETH_PHY=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH_PHY=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH_PHY=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH_PHY=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH_PHY=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_REALTEK=y
CONFIG_RENESAS_RAVB=y
CONFIG_DM_REGULATOR=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_DWC_ETH_QOS=y
CONFIG_KS8851_MLL=y
CONFIG_PHY=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DWC_ETH_QOS=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_FIXED=y
CONFIG_DM_DSA=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_NATSEMI=y
CONFIG_PHY_REALTEK=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_ADIN=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_NATSEMI=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_ADIN=y
CONFIG_PHY_TI_DP83867=y
CONFIG_PHY_XILINX_GMII2RGMII=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_ADIN=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_MICREL=y
if ((i++ % 500) == 0)
printf(".");
} while (!aquantia_link_is_up(phydev) &&
- i < (4 * PHY_ANEG_TIMEOUT));
+ i < (4 * CONFIG_PHY_ANEG_TIMEOUT));
- if (i > PHY_ANEG_TIMEOUT)
+ if (i > CONFIG_PHY_ANEG_TIMEOUT)
printf(" TIMEOUT !\n");
}
/*
* Timeout reached ?
*/
- if (i > (PHY_ANEG_TIMEOUT / 50)) {
+ if (i > (CONFIG_PHY_ANEG_TIMEOUT / 50)) {
printf(" TIMEOUT !\n");
phydev->link = 0;
return -ETIMEDOUT;
* and the external PHY is not obtained.
*/
debug("axiemac: waiting for link status of the PCS/PMA PHY");
- while (retry_cnt * 10 < PHY_ANEG_TIMEOUT) {
+ while (retry_cnt * 10 < CONFIG_PHY_ANEG_TIMEOUT) {
rc = phyread(priv, priv->pcsaddr, MII_BMSR, &mii_reg);
if ((mii_reg & BMSR_LSTATUS) && mii_reg != 0xffff && !rc) {
debug(".Done\n");
#endif
-#define PHY_ANEG_TIMEOUT 8000 /* PHY needs longer aneg time at 1G */
-
/* NAND support */
#ifdef CONFIG_MTD_RAW_NAND
/* NAND: device related configs */
#include <configs/ti_omap5_common.h>
/* CPSW Ethernet */
-#define PHY_ANEG_TIMEOUT 8000 /* PHY needs longer aneg time at 1G */
/*
* Default to using SPI for environment, etc.
#define CFG_SYS_FSL_USDHC_NUM 3
/* Network */
-#define PHY_ANEG_TIMEOUT 15000 /* PHY needs longer aneg time */
/* USB Configs */
/* Host */
* image and environment
*/
-#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
-
/* Keep device tree and initrd in lower memory so the kernel can access them */
#define RELOCATION_LIMITS_ENV_SETTINGS \
"fdt_high=0x10000000\0" \
/* Environment in SPI NOR flash */
-#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
-
/*
* Environment Configuration
*/
/* Environment in SPI NOR flash */
-#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
-
/*
* mv-common.h should be defined after CMD configs since it used them
* to enable certain macros
/* Environment in SPI NOR flash */
-#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
-
/* NAND */
/* Keep device tree and initrd in lower memory so the kernel can access them */
/* Environment in SPI NOR flash */
-#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
-
/* Keep device tree and initrd in lower memory so the kernel can access them */
#define CFG_EXTRA_ENV_SETTINGS \
"fdt_high=0x10000000\0" \
/* Environment in SPI NOR flash */
-#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
-
/* NAND */
/*
#ifndef _CONFIG_DS116_H
#define _CONFIG_DS116_H
-#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
-
/* Keep device tree and initrd in lower memory so the kernel can access them */
#define RELOCATION_LIMITS_ENV_SETTINGS \
"fdt_high=0x10000000\0" \
/* increase autoneg timeout, my NIC sucks */
-#define PHY_ANEG_TIMEOUT 16000
#endif /* _CONFIG_SYNOLOGY_DS414_H */
* image and environment
*/
-#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
-
/* Keep device tree and initrd in lower memory so the kernel can access them */
#define RELOCATION_LIMITS_ENV_SETTINGS \
"fdt_high=0x10000000\0" \
#define __CONFIGS_HMIBSC_H
/* PHY needs a longer aneg time */
-#define PHY_ANEG_TIMEOUT 8000
#define CFG_ENV_FLAGS_LIST_STATIC "BOOT_A_LEFT:dw,BOOT_B_LEFT:dw,BOOT_ORDER:sw"
#include <configs/verdin-imx8mm.h>
/* PHY needs a longer autoneg timeout */
-#define PHY_ANEG_TIMEOUT 20000
/* Custom initial environment variables */
#undef CFG_EXTRA_ENV_SETTINGS
#define CFG_MXC_UART_BASE UART3_BASE_ADDR
/* PHY needs a longer autonegotiation timeout after reset */
-#define PHY_ANEG_TIMEOUT 20000
/* USDHC */
#define CFG_SYS_FSL_USDHC_NUM 2
#define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
-#if defined(CONFIG_CMD_NET)
-#define PHY_ANEG_TIMEOUT 20000
-#endif
-
/* Link Definitions */
#define CFG_SYS_INIT_RAM_ADDR 0x40000000
#define CFG_MXC_UART_BASE UART3_BASE_ADDR
/* PHY needs a longer autonegotiation timeout after reset */
-#define PHY_ANEG_TIMEOUT 20000
#define FEC_QUIRK_ENET_MAC
#define CFG_EXTRA_ENV_SETTINGS \
#if defined(CONFIG_CMD_NET)
#define CFG_FEC_MXC_PHYADDR 1
-#define PHY_ANEG_TIMEOUT 20000
-
#endif
#define BOOT_TARGET_DEVICES(func) \
#define CFG_MXC_UART_BASE UART1_BASE_ADDR
/* PHY needs a longer autonegotiation timeout after reset */
-#define PHY_ANEG_TIMEOUT 20000
#define FEC_QUIRK_ENET_MAC
/* USDHC */
#if defined(CONFIG_CMD_NET)
#define CFG_FEC_MXC_PHYADDR 1
-#define PHY_ANEG_TIMEOUT 20000
-
#endif
#define BOOT_TARGET_DEVICES(func) \
#define DWC_NET_PHYADDR 1
-#define PHY_ANEG_TIMEOUT 20000
-
#endif
#define BOOT_TARGET_DEVICES(func) \
#if defined(CONFIG_CMD_NET)
#define CFG_FEC_MXC_PHYADDR 4
-#define PHY_ANEG_TIMEOUT 20000
-
#endif
#if IS_ENABLED(CONFIG_CMD_MMC)
/* ENET Config */
#if defined(CONFIG_FEC_MXC)
-#define PHY_ANEG_TIMEOUT 20000
-
#define CFG_FEC_MXC_PHYADDR 1
#endif
/* Using ULP WDOG for reset */
#define WDOG_BASE_ADDR WDG3_BASE_ADDR
-#if defined(CONFIG_CMD_NET)
-#define PHY_ANEG_TIMEOUT 20000
-#endif
-
#endif
/* Using ULP WDOG for reset */
#define WDOG_BASE_ADDR WDG3_BASE_ADDR
-#if defined(CONFIG_CMD_NET)
-#define PHY_ANEG_TIMEOUT 20000
-#endif
-
#endif
/* Network */
#define CFG_KSNET_CPSW_NUM_PORTS 2
-#define PHY_ANEG_TIMEOUT 10000 /* PHY needs longer aneg time */
#include <configs/ti_armv7_keystone2.h>
#if defined(CONFIG_CMD_NET)
#define CFG_FEC_MXC_PHYADDR 0
-#define PHY_ANEG_TIMEOUT 20000
-
#endif
#define ENV_MEM_LAYOUT_SETTINGS \
#define DTB_LOAD_ADDR 0x5600000
#define INITRD_LOAD_ADDR 0x5bf0000
/* PHY needs longer aneg time at 1G */
-#define PHY_ANEG_TIMEOUT 8000
#endif
/* Environment in SPI NOR flash */
-#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
-
/*
* mv-common.h should be defined after CMD configs since it used them
* to enable certain macros
#if defined(CONFIG_CMD_NET)
#define CFG_FEC_MXC_PHYADDR 1
-#define PHY_ANEG_TIMEOUT 20000
#endif
#ifndef CONFIG_SPL_BUILD
#ifndef _CONFIG_N2350_H
#define _CONFIG_N2350_H
-#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
-
/* Keep device tree and initrd in lower memory so the kernel can access them */
#define RELOCATION_LIMITS_ENV_SETTINGS \
"fdt_high=0x10000000\0" \
#include "octeon_common.h"
-#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
-
#endif /* __CONFIG_H__ */
/* console */
#define CFG_SYS_BAUDRATE_TABLE { 115200, 38400 }
-/* PHY needs a longer autoneg timeout */
-#define PHY_ANEG_TIMEOUT 20000
-
/* MEMORY */
-
#define DRAM_RSV_SIZE 0x08000000
#define CFG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE)
#define CFG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE)
#define CFG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE)
/* PHY needs a longer autoneg timeout */
-#define PHY_ANEG_TIMEOUT 20000
/* Environment setting */
#define CFG_EXTRA_ENV_SETTINGS \
/* Ethernet on SoC (EMAC) */
/* The PHY is autodetected, so no MII PHY address is needed here */
-#define PHY_ANEG_TIMEOUT 8000
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>
#define __CONFIG_STM32MP15_DH_DHSOM_H__
/* PHY needs a longer autoneg timeout */
-#define PHY_ANEG_TIMEOUT 20000
#ifdef CONFIG_SPL_BUILD
#define CFG_EXTRA_ENV_SETTINGS \
/* Environment in SPI NOR flash */
-#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
-
/* Keep device tree and initrd in lower memory so the kernel can access them */
#define CFG_EXTRA_ENV_SETTINGS \
"fdt_high=0x10000000\0" \
/* Environment in SPI NOR flash */
-#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
-
/* Keep device tree and initrd in lower memory so the kernel can access them */
#define RELOCATION_LIMITS_ENV_SETTINGS \
"fdt_high=0x10000000\0" \
/* Environment in SPI NOR flash */
-#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
-
/* NAND */
#include <asm/arch/config.h>
#endif
/* Ethernet driver */
-#if defined(CONFIG_ZYNQ_GEM)
-# define PHY_ANEG_TIMEOUT 20000
-#endif
#define ENV_MEM_LAYOUT_SETTINGS \
"fdt_addr_r=0x40000000\0" \
#endif
/* Ethernet driver */
-#if defined(CONFIG_ZYNQ_GEM)
-# define PHY_ANEG_TIMEOUT 20000
-#endif
#define ENV_MEM_LAYOUT_SETTINGS \
"fdt_addr_r=0x40000000\0" \
/* Console I/O Buffer Size */
/* Ethernet driver */
-#if defined(CONFIG_ZYNQ_GEM)
-# define PHY_ANEG_TIMEOUT 20000
-#endif
#define ENV_MEM_LAYOUT_SETTINGS \
"fdt_addr_r=0x40000000\0" \
#define PHY_10G_FEATURES (PHY_GBIT_FEATURES | \
SUPPORTED_10000baseT_Full)
-#ifndef PHY_ANEG_TIMEOUT
-#define PHY_ANEG_TIMEOUT CONFIG_PHY_ANEG_TIMEOUT
-#endif
-
struct phy_device;
#define MDIO_NAME_LEN 32