board: freescale: t208xrdb: enable Power-On Reset for rev D boards

Starting with board revision D, the MISCCSR CPLD register needs to be
configured to enable Power-on Reset for software reset commands.

Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>

diff --git a/board/freescale/t208xrdb/cpld.h b/board/freescale/t208xrdb/cpld.h
index a623b1811faff8fc8622f2ff0a31f0a101e9d899..3139c2b85fd16d24cd335710f7f3d2dcda5bd994 100644 (file)
--- a/board/freescale/t208xrdb/cpld.h
+++ b/board/freescale/t208xrdb/cpld.h
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2014 Freescale Semiconductor
+ * Copyright 2021 NXP
  */
 
 /*
@@ -42,3 +43,6 @@ void cpld_write(unsigned int reg, u8 value);
 
 /* RSTCON Register */
 #define CPLD_RSTCON_EDC_RST    0x04
+
+/* MISCCSR Register */
+#define CPLD_MISC_POR_EN       0x30

diff --git a/board/freescale/t208xrdb/t208xrdb.c b/board/freescale/t208xrdb/t208xrdb.c
index 1f0cdee0b8634b4f2c0b8f73b9e385322ba075ee..947dd6aa9f3aa5cefeb2e49ec7d43ffd78a7352b 100644 (file)
--- a/board/freescale/t208xrdb/t208xrdb.c
+++ b/board/freescale/t208xrdb/t208xrdb.c
@@ -128,6 +128,13 @@ int misc_init_r(void)
        reg |= CPLD_RSTCON_EDC_RST;
        CPLD_WRITE(reset_ctl, reg);
 
+       /* Enable POR for boards revisions D and up */
+       if (get_hw_revision() >= 'D') {
+               reg = CPLD_READ(misc_csr);
+               reg |= CPLD_MISC_POR_EN;
+               CPLD_WRITE(misc_csr, reg);
+       }
+
        return 0;
 }