arm: dts: rockchip: rk3128: fix clocks, compatible and phys

Fix rk3128 clocks, compatible and phys, so that they match the bindings.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>

diff --git a/arch/arm/dts/rk3128.dtsi b/arch/arm/dts/rk3128.dtsi
index 48833bff9eef9f4de2ab614f8bd42e3512ef35c6..3253c6403413423fa2f71473d5e3811566dc7190 100644 (file)
--- a/arch/arm/dts/rk3128.dtsi
+++ b/arch/arm/dts/rk3128.dtsi
@@ -180,7 +180,6 @@
 
        xin12m: xin12m {
                compatible = "fixed-clock";
-               clocks = <&xin24m>;
                clock-frequency = <12000000>;
                clock-output-names = "xin12m";
                #clock-cells = <0>;
@@ -202,9 +201,9 @@
        };
 
        watchdog: watchdog@2004c000 {
-               compatible = "rockchip,watch dog";
+               compatible = "rockchip,rk3128-wdt", "snps,dw-wdt";
                reg = <0x2004c000 0x100>;
-               clock-names = "pclk_wdt";
+               clocks = <&cru PCLK_WDT>;
                interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
                rockchip,irq = <1>;
                rockchip,timeout = <60>;
@@ -219,21 +218,20 @@
        };
 
        nandc: nand-controller@10500000 {
-               compatible = "rockchip,rk-nandc";
+               compatible = "rockchip,rk3128-nfc", "rockchip,rk2928-nfc";
                reg = <0x10500000 0x4000>;
                interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
                pinctrl-names = "default";
                pinctrl-0 = <&nandc_ale &nandc_cle &nandc_wrn &nandc_rdn &nandc_rdy &nandc_cs0 &nandc_data>;
-               nandc_id = <0>;
-               clocks = <&cru SCLK_NANDC>,
-                        <&cru HCLK_NANDC>,
-                        <&cru SRST_NANDC>;
-               clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
+               clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
+               clock-names = "ahb", "nfc";
        };
 
        cru: clock-controller@20000000 {
                compatible = "rockchip,rk3128-cru";
                reg = <0x20000000 0x1000>;
+               clocks = <&xin24m>;
+               clock-names = "xin24m";
                rockchip,grf = <&grf>;
                #clock-cells = <1>;
                #reset-cells = <1>;
@@ -305,7 +303,6 @@
                pinctrl-names = "default";
                pinctrl-0 = <&pwm0_pin>;
                clocks = <&cru PCLK_PWM>;
-               clock-names = "pwm";
        };
 
        pwm1: pwm@20050010 {
@@ -315,7 +312,6 @@
                pinctrl-names = "default";
                pinctrl-0 = <&pwm1_pin>;
                clocks = <&cru PCLK_PWM>;
-               clock-names = "pwm";
        };
 
        pwm2: pwm@20050020 {
@@ -325,7 +321,6 @@
                pinctrl-names = "default";
                pinctrl-0 = <&pwm2_pin>;
                clocks = <&cru PCLK_PWM>;
-               clock-names = "pwm";
        };
 
        pwm3: pwm@20050030 {
@@ -335,7 +330,6 @@
                pinctrl-names = "default";
                pinctrl-0 = <&pwm3_pin>;
                clocks = <&cru PCLK_PWM>;
-               clock-names = "pwm";
        };
 
        sram: sram@10080400 {
@@ -364,7 +358,7 @@
                interrupts = <GIC_PPI 9 0xf04>;
        };
 
-       u2phy: usb2-phy {
+       u2phy: usb2phy {
                compatible = "rockchip,rk3128-usb2phy";
                reg = <0x017c 0x0c>;
                rockchip,grf = <&grf>;
@@ -372,7 +366,6 @@
                clock-names = "phyclk";
                #clock-cells = <0>;
                clock-output-names = "usb480m_phy";
-               #phy-cells = <1>;
                status = "disabled";
 
                u2phy_otg: otg-port {
@@ -394,15 +387,14 @@
        };
 
        usb_otg: usb@10180000 {
-               compatible = "rockchip,rk3128-usb", "rockchip,rk3288-usb",
-                            "snps,dwc2";
+               compatible = "rockchip,rk3128-usb", "rockchip,rk3066-usb", "snps,dwc2";
                reg = <0x10180000 0x40000>;
                interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cru HCLK_OTG>;
+               clock-names = "otg";
                dr_mode = "otg";
-               g-use-dma;
-               hnp-srp-disable;
-               phys = <&u2phy 0>;
-               phy-names = "usb";
+               phys = <&u2phy_otg>;
+               phy-names = "usb2-phy";
                status = "disabled";
        };
 
@@ -410,7 +402,7 @@
                compatible = "generic-ehci";
                reg = <0x101c0000 0x20000>;
                interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
-               phys = <&u2phy 1>;
+               phys = <&u2phy_host>;
                phy-names = "usb";
                status = "disabled";
        };
@@ -419,19 +411,19 @@
                compatible = "generic-ohci";
                reg = <0x101e0000 0x20000>;
                interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-               phys = <&u2phy 1>;
+               phys = <&u2phy_host>;
                phy-names = "usb";
                status = "disabled";
        };
 
        sdmmc: mmc@10214000 {
-               compatible = "rockchip,rk312x-dw-mshc", "rockchip,rk3288-dw-mshc";
+               compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
                reg = <0x10214000 0x4000>;
                max-frequency = <150000000>;
                interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
                         <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
-               clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+               clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
                fifo-depth = <0x100>;
                pinctrl-names = "default";
                pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
@@ -446,7 +438,7 @@
                interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
                         <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
-               clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+               clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
                bus-width = <8>;
                default-sample-phase = <158>;
                num-slots = <1>;
@@ -507,7 +499,7 @@
        };
 
        spi0: spi@20074000 {
-               compatible = "rockchip,rk3128-spi", "rockchip,rk3288-spi";
+               compatible = "rockchip,rk3128-spi", "rockchip,rk3066-spi";
                reg = <0x20074000 0x1000>;
                interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
                #address-cells = <1>;