x86: ivybridge: Fix PCH power setup

At present pch_power_options() has the arguments to writel() around the
wrong way. Fix this and update it to compile on 64-bit machines.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c
index 4e0be2a88b907b41beacfe5d0d8e199eb23c8538..91c9c0e35e878289c73c24422b64b0485f9c8aae 100644 (file)
--- a/arch/x86/cpu/ivybridge/lpc.c
+++ b/arch/x86/cpu/ivybridge/lpc.c
@@ -213,10 +213,10 @@ static int pch_power_options(struct udevice *pch)
        dm_pci_read_config16(pch, 0x40, &pmbase);
        pmbase &= 0xfffe;
 
-       writel(pmbase + GPE0_EN, fdtdec_get_int(blob, node,
-                                               "intel,gpe0-enable", 0));
-       writew(pmbase + ALT_GP_SMI_EN, fdtdec_get_int(blob, node,
-                                               "intel,alt-gp-smi-enable", 0));
+       writel(fdtdec_get_int(blob, node, "intel,gpe0-enable", 0),
+              (ulong)pmbase + GPE0_EN);
+       writew(fdtdec_get_int(blob, node, "intel,alt-gp-smi-enable", 0),
+              (ulong)pmbase + ALT_GP_SMI_EN);
 
        /* Set up power management block and determine sleep mode */
        reg32 = inl(pmbase + 0x04); /* PM1_CNT */