ARM64: zynqmp: Add support for USB ulpi phy reset via mode pins

Mode pins can be used as output for reset. Xilinx boards are using
this feature as additional way how to reset USB phys and also others
chips on the boards.
Mode1 is used on all these boards for this feature.
Let SPL toggle reset on this pin by default.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/cpu/armv8/zynqmp/spl.c b/arch/arm/cpu/armv8/zynqmp/spl.c
index 3ad5de1408786a191cdd032e512d987d23a3ff0f..552f577b95d24494046feb2e59a581ff60c01ea9 100644 (file)
--- a/arch/arm/cpu/armv8/zynqmp/spl.c
+++ b/arch/arm/cpu/armv8/zynqmp/spl.c
@@ -35,10 +35,33 @@ void board_init_f(ulong dummy)
        board_init_r(NULL, 0);
 }
 
+static void ps_mode_reset(ulong mode)
+{
+       writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT |
+              mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT,
+              &crlapb_base->boot_pin_ctrl);
+       udelay(1);
+       writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT,
+              &crlapb_base->boot_pin_ctrl);
+       udelay(5);
+       writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT |
+              mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT,
+              &crlapb_base->boot_pin_ctrl);
+}
+
+/*
+ * Set default PS_MODE1 which is used for USB ULPI phy reset
+ * Also other resets can be connected to this certain pin
+ */
+#ifndef MODE_RESET
+# define MODE_RESET    PS_MODE1
+#endif
+
 #ifdef CONFIG_SPL_BOARD_INIT
 void spl_board_init(void)
 {
        preloader_console_init();
+       ps_mode_reset(MODE_RESET);
        board_init();
 }
 #endif

diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h
index 10d67d0fb7b05bee1b4196e32e2609ba89794450..456c1b0902e578c985dba3af3115873863102748 100644 (file)
--- a/arch/arm/include/asm/arch-zynqmp/hardware.h
+++ b/arch/arm/include/asm/arch-zynqmp/hardware.h
@@ -25,6 +25,13 @@
 
 #define ZYNQMP_CRL_APB_BASEADDR        0xFF5E0000
 #define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT       0x1000000
+#define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT      0
+#define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT     8
+
+#define PS_MODE0       BIT(0)
+#define PS_MODE1       BIT(1)
+#define PS_MODE2       BIT(2)
+#define PS_MODE3       BIT(3)
 
 struct crlapb_regs {
        u32 reserved0[36];
@@ -35,7 +42,9 @@ struct crlapb_regs {
        u32 boot_mode; /* 0x200 */
        u32 reserved3[14];
        u32 rst_lpd_top; /* 0x23C */
-       u32 reserved4[26];
+       u32 reserved4[4];
+       u32 boot_pin_ctrl; /* 0x250 */
+       u32 reserved5[21];
 };
 
 #define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR)