arm: mach-omap2: am33xx: Add device structure for spi

Add platform data and a device structure for the spi device
present on am335x-icev2. This requires moving all omap3_spi
platform data structures and symbols to an omap3_spi.h so that
the board file can access them.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>

diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c
index a7b56b6bb3de00dbff7bbb475505fc061318a789..2888390d24038ce7f619cebb28d67d91b5ddd9fb 100644 (file)
--- a/arch/arm/mach-omap2/am33xx/board.c
+++ b/arch/arm/mach-omap2/am33xx/board.c
@@ -14,6 +14,7 @@
 #include <init.h>
 #include <net.h>
 #include <ns16550.h>
+#include <omap3_spi.h>
 #include <spl.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/hardware.h>
@@ -49,6 +50,12 @@
 #define AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET         0xDC
 #define AM43XX_RDWRLVLFULL_START                       0x80000000
 
+/* SPI flash. */
+#if CONFIG_IS_ENABLED(DM_SPI) && !CONFIG_IS_ENABLED(OF_CONTROL)
+#define AM33XX_SPI0_BASE       0x48030000
+#define AM33XX_SPI0_OFFSET     (AM33XX_SPI0_BASE + OMAP4_MCSPI_REG_OFFSET)
+#endif
+
 DECLARE_GLOBAL_DATA_PTR;
 
 int dram_init(void)
@@ -142,6 +149,17 @@ U_BOOT_DEVICES(am33xx_gpios) = {
 #endif
 };
 #endif
+#if CONFIG_IS_ENABLED(DM_SPI) && !CONFIG_IS_ENABLED(OF_CONTROL)
+static const struct omap3_spi_plat omap3_spi_pdata = {
+       .regs = (struct mcspi *)AM33XX_SPI0_OFFSET,
+       .pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT,
+};
+
+U_BOOT_DEVICE(am33xx_spi) = {
+       .name = "omap3_spi",
+       .platdata = &omap3_spi_pdata,
+};
+#endif
 #endif
 
 #if !CONFIG_IS_ENABLED(DM_GPIO)

diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c
index fbf9575851a907099a928fd19aee4a0a6ece5f79..fb1cf360fcd0413b1dcaf743ae1b86e9625453c1 100644 (file)
--- a/drivers/spi/omap3_spi.c
+++ b/drivers/spi/omap3_spi.c
@@ -22,82 +22,14 @@
 #include <malloc.h>
 #include <asm/io.h>
 #include <linux/bitops.h>
+#include <omap3_spi.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define OMAP4_MCSPI_REG_OFFSET 0x100
-
 struct omap2_mcspi_platform_config {
        unsigned int regs_offset;
 };
 
-/* per-register bitmasks */
-#define OMAP3_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3)
-#define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2)
-#define OMAP3_MCSPI_SYSCONFIG_AUTOIDLE BIT(0)
-#define OMAP3_MCSPI_SYSCONFIG_SOFTRESET BIT(1)
-
-#define OMAP3_MCSPI_SYSSTATUS_RESETDONE BIT(0)
-
-#define OMAP3_MCSPI_MODULCTRL_SINGLE   BIT(0)
-#define OMAP3_MCSPI_MODULCTRL_MS       BIT(2)
-#define OMAP3_MCSPI_MODULCTRL_STEST    BIT(3)
-
-#define OMAP3_MCSPI_CHCONF_PHA         BIT(0)
-#define OMAP3_MCSPI_CHCONF_POL         BIT(1)
-#define OMAP3_MCSPI_CHCONF_CLKD_MASK   GENMASK(5, 2)
-#define OMAP3_MCSPI_CHCONF_EPOL                BIT(6)
-#define OMAP3_MCSPI_CHCONF_WL_MASK     GENMASK(11, 7)
-#define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
-#define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
-#define OMAP3_MCSPI_CHCONF_TRM_MASK    GENMASK(13, 12)
-#define OMAP3_MCSPI_CHCONF_DMAW                BIT(14)
-#define OMAP3_MCSPI_CHCONF_DMAR                BIT(15)
-#define OMAP3_MCSPI_CHCONF_DPE0                BIT(16)
-#define OMAP3_MCSPI_CHCONF_DPE1                BIT(17)
-#define OMAP3_MCSPI_CHCONF_IS          BIT(18)
-#define OMAP3_MCSPI_CHCONF_TURBO       BIT(19)
-#define OMAP3_MCSPI_CHCONF_FORCE       BIT(20)
-
-#define OMAP3_MCSPI_CHSTAT_RXS         BIT(0)
-#define OMAP3_MCSPI_CHSTAT_TXS         BIT(1)
-#define OMAP3_MCSPI_CHSTAT_EOT         BIT(2)
-
-#define OMAP3_MCSPI_CHCTRL_EN          BIT(0)
-#define OMAP3_MCSPI_CHCTRL_DIS         (0 << 0)
-
-#define OMAP3_MCSPI_WAKEUPENABLE_WKEN  BIT(0)
-#define MCSPI_PINDIR_D0_IN_D1_OUT      0
-#define MCSPI_PINDIR_D0_OUT_D1_IN      1
-
-#define OMAP3_MCSPI_MAX_FREQ           48000000
-#define SPI_WAIT_TIMEOUT               10
-
-/* OMAP3 McSPI registers */
-struct mcspi_channel {
-       unsigned int chconf;            /* 0x2C, 0x40, 0x54, 0x68 */
-       unsigned int chstat;            /* 0x30, 0x44, 0x58, 0x6C */
-       unsigned int chctrl;            /* 0x34, 0x48, 0x5C, 0x70 */
-       unsigned int tx;                /* 0x38, 0x4C, 0x60, 0x74 */
-       unsigned int rx;                /* 0x3C, 0x50, 0x64, 0x78 */
-};
-
-struct mcspi {
-       unsigned char res1[0x10];
-       unsigned int sysconfig;         /* 0x10 */
-       unsigned int sysstatus;         /* 0x14 */
-       unsigned int irqstatus;         /* 0x18 */
-       unsigned int irqenable;         /* 0x1C */
-       unsigned int wakeupenable;      /* 0x20 */
-       unsigned int syst;              /* 0x24 */
-       unsigned int modulctrl;         /* 0x28 */
-       struct mcspi_channel channel[4];
-       /* channel0: 0x2C - 0x3C, bus 0 & 1 & 2 & 3 */
-       /* channel1: 0x40 - 0x50, bus 0 & 1 */
-       /* channel2: 0x54 - 0x64, bus 0 & 1 */
-       /* channel3: 0x68 - 0x78, bus 0 */
-};
-
 struct omap3_spi_priv {
        struct mcspi *regs;
        unsigned int cs;

diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index 103c046137465ae49ba5d207f349abf6ae28f425..5af90d932d5c603c6684b98c5b76a42dd229de03 100644 (file)
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -287,8 +287,6 @@
 #define CONFIG_SYS_ENV_SECT_SIZE       CONFIG_SYS_NAND_BLOCK_SIZE
 #endif
 
-/* SPI flash. */
-
 /* Network. */
 /* Enable Atheros phy driver */
 

diff --git a/include/omap3_spi.h b/include/omap3_spi.h
new file mode 100644 (file)
index 0000000..cae3770
--- /dev/null
+++ b/include/omap3_spi.h
@@ -0,0 +1,78 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+#ifndef __OMAP3_SPI_H_
+#define __OMAP3_SPI_H_
+
+/* per-register bitmasks */
+#define OMAP3_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3)
+#define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2)
+#define OMAP3_MCSPI_SYSCONFIG_AUTOIDLE BIT(0)
+#define OMAP3_MCSPI_SYSCONFIG_SOFTRESET BIT(1)
+
+#define OMAP3_MCSPI_SYSSTATUS_RESETDONE BIT(0)
+
+#define OMAP3_MCSPI_MODULCTRL_SINGLE   BIT(0)
+#define OMAP3_MCSPI_MODULCTRL_MS       BIT(2)
+#define OMAP3_MCSPI_MODULCTRL_STEST    BIT(3)
+
+#define OMAP3_MCSPI_CHCONF_PHA         BIT(0)
+#define OMAP3_MCSPI_CHCONF_POL         BIT(1)
+#define OMAP3_MCSPI_CHCONF_CLKD_MASK   GENMASK(5, 2)
+#define OMAP3_MCSPI_CHCONF_EPOL                BIT(6)
+#define OMAP3_MCSPI_CHCONF_WL_MASK     GENMASK(11, 7)
+#define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
+#define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
+#define OMAP3_MCSPI_CHCONF_TRM_MASK    GENMASK(13, 12)
+#define OMAP3_MCSPI_CHCONF_DMAW                BIT(14)
+#define OMAP3_MCSPI_CHCONF_DMAR                BIT(15)
+#define OMAP3_MCSPI_CHCONF_DPE0                BIT(16)
+#define OMAP3_MCSPI_CHCONF_DPE1                BIT(17)
+#define OMAP3_MCSPI_CHCONF_IS          BIT(18)
+#define OMAP3_MCSPI_CHCONF_TURBO       BIT(19)
+#define OMAP3_MCSPI_CHCONF_FORCE       BIT(20)
+
+#define OMAP3_MCSPI_CHSTAT_RXS         BIT(0)
+#define OMAP3_MCSPI_CHSTAT_TXS         BIT(1)
+#define OMAP3_MCSPI_CHSTAT_EOT         BIT(2)
+
+#define OMAP3_MCSPI_CHCTRL_EN          BIT(0)
+#define OMAP3_MCSPI_CHCTRL_DIS         (0 << 0)
+
+#define OMAP3_MCSPI_WAKEUPENABLE_WKEN  BIT(0)
+#define MCSPI_PINDIR_D0_IN_D1_OUT      0
+#define MCSPI_PINDIR_D0_OUT_D1_IN      1
+
+#define OMAP3_MCSPI_MAX_FREQ           48000000
+#define SPI_WAIT_TIMEOUT               10
+
+#define OMAP4_MCSPI_REG_OFFSET 0x100
+
+/* OMAP3 McSPI registers */
+struct mcspi_channel {
+       unsigned int chconf;            /* 0x2C, 0x40, 0x54, 0x68 */
+       unsigned int chstat;            /* 0x30, 0x44, 0x58, 0x6C */
+       unsigned int chctrl;            /* 0x34, 0x48, 0x5C, 0x70 */
+       unsigned int tx;                /* 0x38, 0x4C, 0x60, 0x74 */
+       unsigned int rx;                /* 0x3C, 0x50, 0x64, 0x78 */
+};
+
+struct mcspi {
+       unsigned char res1[0x10];
+       unsigned int sysconfig;         /* 0x10 */
+       unsigned int sysstatus;         /* 0x14 */
+       unsigned int irqstatus;         /* 0x18 */
+       unsigned int irqenable;         /* 0x1C */
+       unsigned int wakeupenable;      /* 0x20 */
+       unsigned int syst;              /* 0x24 */
+       unsigned int modulctrl;         /* 0x28 */
+       struct mcspi_channel channel[4];
+       /* channel0: 0x2C - 0x3C, bus 0 & 1 & 2 & 3 */
+       /* channel1: 0x40 - 0x50, bus 0 & 1 */
+       /* channel2: 0x54 - 0x64, bus 0 & 1 */
+       /* channel3: 0x68 - 0x78, bus 0 */
+};
+
+struct omap3_spi_plat {
+       struct mcspi *regs;
+       unsigned int pin_dir:1;
+};
+#endif