]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
global: Migrate CONFIG_RESET_VECTOR_ADDRESS to CFG
authorTom Rini <trini@konsulko.com>
Sun, 4 Dec 2022 15:13:40 +0000 (10:13 -0500)
committerTom Rini <trini@konsulko.com>
Fri, 23 Dec 2022 15:15:11 +0000 (10:15 -0500)
Perform a simple rename of CONFIG_RESET_VECTOR_ADDRESS to CFG_RESET_VECTOR_ADDRESS

Signed-off-by: Tom Rini <trini@konsulko.com>
18 files changed:
arch/powerpc/cpu/mpc85xx/Kconfig
arch/powerpc/cpu/mpc85xx/u-boot.lds
arch/powerpc/dts/kmcent2-u-boot.dtsi
arch/powerpc/dts/u-boot.dtsi
board/freescale/p1_p2_rdb_pc/README
board/freescale/p2041rdb/README
board/freescale/t104xrdb/README
board/freescale/t208xqds/README
board/freescale/t208xrdb/README
include/configs/P1010RDB.h
include/configs/P2041RDB.h
include/configs/T102xRDB.h
include/configs/T104xRDB.h
include/configs/T208xQDS.h
include/configs/T208xRDB.h
include/configs/T4240RDB.h
include/configs/kmcent2.h
include/configs/p1_p2_rdb_pc.h

index 3275d4fa9b88af5309884b8a48344019ffc922ed..6ab8a5249a42dd6df1d31f9cb0f7431ab8981d6e 100644 (file)
@@ -931,7 +931,7 @@ config ARCH_T4240
        imply FSL_SATA
 
 config MPC85XX_HAVE_RESET_VECTOR
-       bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc"
+       bool "Indicate reset vector at CFG_RESET_VECTOR_ADDRESS - 0xffc"
        depends on MPC85xx
 
 config BTB
index fa3aa954cbb5ae57b28266f94c20cf7a1d7a1c85..3af0dfdf336b9453535197e1a6af24c4359b265d 100644 (file)
@@ -5,8 +5,8 @@
 
 #include "config.h"
 
-#ifdef CONFIG_RESET_VECTOR_ADDRESS
-#define RESET_VECTOR_ADDRESS   CONFIG_RESET_VECTOR_ADDRESS
+#ifdef CFG_RESET_VECTOR_ADDRESS
+#define RESET_VECTOR_ADDRESS   CFG_RESET_VECTOR_ADDRESS
 #else
 #define RESET_VECTOR_ADDRESS   0xfffffffc
 #endif
index 28f303b749e98e461f56d3470392a37a054ea2d3..53bac5533f2427c9fa7c937d4134a6b51813b3a9 100644 (file)
@@ -91,7 +91,7 @@
                        align = <256>;
                };
                powerpc-mpc85xx-bootpg-resetvec {
-                       offset = <(CONFIG_RESET_VECTOR_ADDRESS - 0xffc)>;
+                       offset = <(CFG_RESET_VECTOR_ADDRESS - 0xffc)>;
                };
        };
 };
index b4b5257362e573aec556d1d84b61167d31bbf428..6b7375cff2150e18f4fa7c8a83ce88d3e080cdfd 100644 (file)
                u-boot-dtb-with-ucode {
                        align = <4>;
                };
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#ifndef CFG_RESET_VECTOR_ADDRESS
+#define CFG_RESET_VECTOR_ADDRESS 0xfffffffc
 #endif
                powerpc-mpc85xx-bootpg-resetvec {
-                       offset = <(CONFIG_RESET_VECTOR_ADDRESS - 0xffc)>;
+                       offset = <(CFG_RESET_VECTOR_ADDRESS - 0xffc)>;
                };
        };
 };
index f542decec79bd996cffadfbd0f05d0a3f2c6fcc6..fd849bfc29a2c30fdf60fd2d0953444fdeade80a 100644 (file)
@@ -57,7 +57,7 @@ enabled in relative defconfig file,
 1. CONFIG_DEFAULT_DEVICE_TREE="p1020rdb" (Change default device tree name if required)
 2. CONFIG_OF_CONTROL
 3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
-   CONFIG_RESET_VECTOR_ADDRESS - 0xffc
+   CFG_RESET_VECTOR_ADDRESS - 0xffc
 
 If device tree support is enabled in defconfig,
 1. use 'u-boot.bin' for NOR boot.
index 96612daeeb111d096b5224f30ddd347c24e221c2..ae77027737232279a5c39eee2b67fcc3f196d907 100644 (file)
@@ -98,7 +98,7 @@ enabled in relative defconfig file,
 1. CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" (Change default device tree name if required)
 2. CONFIG_OF_CONTROL
 3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
-   CONFIG_RESET_VECTOR_ADDRESS - 0xffc
+   CFG_RESET_VECTOR_ADDRESS - 0xffc
 
 CPLD command
 ============
index e90dca416639aa44506ad2e0b27c411f2bf34d1d..f312e6a3e32b409f77eb96008ea883afe4ce1553 100644 (file)
@@ -379,7 +379,7 @@ enabled in relative defconfig file,
 1. CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb" (Change default device tree name if required)
 2. CONFIG_OF_CONTROL
 3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
-   CONFIG_RESET_VECTOR_ADDRESS - 0xffc
+   CFG_RESET_VECTOR_ADDRESS - 0xffc
 
 If device tree support is enabled in defconfig,
 1. use 'u-boot.bin' for NOR boot.
index 63953d6b9b66095f6fba88e3bab9ed82b290c166..0d80c6901fb251be9a82fc9377de0438d199ed51 100755 (executable)
@@ -285,7 +285,7 @@ enabled in relative defconfig file,
 1. CONFIG_DEFAULT_DEVICE_TREE="t2080qds" (Change default device tree name if required)
 2. CONFIG_OF_CONTROL
 3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
-   CONFIG_RESET_VECTOR_ADDRESS - 0xffc
+   CFG_RESET_VECTOR_ADDRESS - 0xffc
 
 If device tree support is enabled in defconfig,
 1. use 'u-boot.bin' for NOR boot.
index 60551f6723e60df1bb9d16ab5ea850c8f58ce6f7..533054bfe192a6d5a184602be260e2b7c0cffc36 100644 (file)
@@ -281,7 +281,7 @@ enabled in relative defconfig file,
 1. CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" (Change default device tree name if required)
 2. CONFIG_OF_CONTROL
 3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
-   CONFIG_RESET_VECTOR_ADDRESS - 0xffc
+   CFG_RESET_VECTOR_ADDRESS - 0xffc
 
 If device tree support is enabled in defconfig,
 1. use 'u-boot.bin' for NOR boot.
index b57e8638ab71cac7b7fca6fb9d7d9841e0de2b0a..9efae58ce903c069f944d2c5a37a84adf3db42b0 100644 (file)
@@ -24,7 +24,7 @@
 
 #ifdef CONFIG_SPIFLASH
 #ifdef CONFIG_NXP_ESBC
-#define CONFIG_RESET_VECTOR_ADDRESS    0x110bfffc
+#define CFG_RESET_VECTOR_ADDRESS       0x110bfffc
 #else
 #define CFG_SYS_SPI_FLASH_U_BOOT_SIZE  (512 << 10)
 #define CFG_SYS_SPI_FLASH_U_BOOT_DST           (0x11000000)
 #endif
 
 #ifdef CONFIG_NAND_SECBOOT     /* NAND Boot */
-#define CONFIG_RESET_VECTOR_ADDRESS    0x110bfffc
+#define CFG_RESET_VECTOR_ADDRESS       0x110bfffc
 #endif
 
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS    0xeffffffc
+#ifndef CFG_RESET_VECTOR_ADDRESS
+#define CFG_RESET_VECTOR_ADDRESS       0xeffffffc
 #endif
 
 /* High Level Configuration Options */
index 6e755fc0a8f5a3af78de9d0f90c01dd85f70cd94..28f53ae78a1cc99ac969fe37fe435f210fce1afa 100644 (file)
@@ -12,7 +12,7 @@
 #define __CONFIG_H
 
 #ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_RESET_VECTOR_ADDRESS    0xfffffffc
+#define CFG_RESET_VECTOR_ADDRESS       0xfffffffc
 #endif
 
 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 #define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
 #define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
                (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
-#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#define CFG_RESET_VECTOR_ADDRESS 0xfffffffc
 #endif
 
 /* High Level Configuration Options */
 
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS    0xeffffffc
+#ifndef CFG_RESET_VECTOR_ADDRESS
+#define CFG_RESET_VECTOR_ADDRESS       0xeffffffc
 #endif
 
 #define CFG_SYS_NUM_CPC                CONFIG_SYS_NUM_DDR_CTLRS
index 063b864f9ff0e069bfca0d3c91dfb89888cb066b..7ee46abffdb64d904025afee200eb1c79169e795 100644 (file)
@@ -28,7 +28,7 @@
 #endif
 
 #ifdef CONFIG_SPIFLASH
-#define CONFIG_RESET_VECTOR_ADDRESS            0x30000FFC
+#define CFG_RESET_VECTOR_ADDRESS               0x30000FFC
 #define CFG_SYS_SPI_FLASH_U_BOOT_SIZE  (768 << 10)
 #define CFG_SYS_SPI_FLASH_U_BOOT_DST           (0x30000000)
 #define CFG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
@@ -36,7 +36,7 @@
 #endif
 
 #ifdef CONFIG_SDCARD
-#define CONFIG_RESET_VECTOR_ADDRESS    0x30000FFC
+#define CFG_RESET_VECTOR_ADDRESS       0x30000FFC
 #define CFG_SYS_MMC_U_BOOT_SIZE        (768 << 10)
 #define CFG_SYS_MMC_U_BOOT_DST (0x30000000)
 #define CFG_SYS_MMC_U_BOOT_START       (0x30000000)
@@ -45,8 +45,8 @@
 
 #endif /* CONFIG_RAMBOOT_PBL */
 
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS    0xeffffffc
+#ifndef CFG_RESET_VECTOR_ADDRESS
+#define CFG_RESET_VECTOR_ADDRESS       0xeffffffc
 #endif
 
 /*
@@ -87,7 +87,7 @@
 #define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
 #define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
                (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
-#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#define CFG_RESET_VECTOR_ADDRESS 0xfffffffc
 #endif
 
 /*
index 9d04d30a53879f1d5e245049ac564650c72156a5..f196bd76e6ecd73f81e0c96656a4948fce13b7fa 100644 (file)
@@ -29,7 +29,7 @@
 #endif
 
 #ifdef CONFIG_SPIFLASH
-#define        CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
+#define        CFG_RESET_VECTOR_ADDRESS                0x30000FFC
 #define CFG_SYS_SPI_FLASH_U_BOOT_SIZE  (768 << 10)
 #define CFG_SYS_SPI_FLASH_U_BOOT_DST           (0x30000000)
 #define CFG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
@@ -37,7 +37,7 @@
 #endif
 
 #ifdef CONFIG_SDCARD
-#define        CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
+#define        CFG_RESET_VECTOR_ADDRESS                0x30000FFC
 #define CFG_SYS_MMC_U_BOOT_SIZE        (768 << 10)
 #define CFG_SYS_MMC_U_BOOT_DST (0x30000000)
 #define CFG_SYS_MMC_U_BOOT_START       (0x30000000)
@@ -48,8 +48,8 @@
 
 /* High Level Configuration Options */
 
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS    0xeffffffc
+#ifndef CFG_RESET_VECTOR_ADDRESS
+#define CFG_RESET_VECTOR_ADDRESS       0xeffffffc
 #endif
 
 #define CFG_SYS_NUM_CPC                CONFIG_SYS_NUM_DDR_CTLRS
index 3b98d25aa47ab712aee581efba0a28a1aa545ac3..2023d7497f69b9119cc4ff5709e5c70315762042 100644 (file)
@@ -30,7 +30,7 @@
 #endif
 
 #ifdef CONFIG_SPIFLASH
-#define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
+#define        CFG_RESET_VECTOR_ADDRESS                0x200FFC
 #define CFG_SYS_SPI_FLASH_U_BOOT_SIZE  (768 << 10)
 #define CFG_SYS_SPI_FLASH_U_BOOT_DST           (0x00200000)
 #define CFG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
@@ -38,7 +38,7 @@
 #endif
 
 #ifdef CONFIG_SDCARD
-#define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
+#define        CFG_RESET_VECTOR_ADDRESS                0x200FFC
 #define CFG_SYS_MMC_U_BOOT_SIZE        (768 << 10)
 #define CFG_SYS_MMC_U_BOOT_DST (0x00200000)
 #define CFG_SYS_MMC_U_BOOT_START       (0x00200000)
 #define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
 #define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
                (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
-#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#define CFG_RESET_VECTOR_ADDRESS 0xfffffffc
 #endif
 
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS    0xeffffffc
+#ifndef CFG_RESET_VECTOR_ADDRESS
+#define CFG_RESET_VECTOR_ADDRESS       0xeffffffc
 #endif
 
 /*
index 60c2947bfc1dba41a47be7f8a30655b522c5d05f..f213d2de770c2e7b7b1eeb0aeb115ddf3509ac28 100644 (file)
@@ -30,7 +30,7 @@
 #endif
 
 #ifdef CONFIG_SPIFLASH
-#define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
+#define        CFG_RESET_VECTOR_ADDRESS             0x200FFC
 #define CFG_SYS_SPI_FLASH_U_BOOT_SIZE       (768 << 10)
 #define CFG_SYS_SPI_FLASH_U_BOOT_DST                (0x00200000)
 #define CFG_SYS_SPI_FLASH_U_BOOT_START      (0x00200000)
@@ -38,7 +38,7 @@
 #endif
 
 #ifdef CONFIG_SDCARD
-#define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
+#define        CFG_RESET_VECTOR_ADDRESS             0x200FFC
 #define CFG_SYS_MMC_U_BOOT_SIZE     (768 << 10)
 #define CFG_SYS_MMC_U_BOOT_DST      (0x00200000)
 #define CFG_SYS_MMC_U_BOOT_START    (0x00200000)
 #define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
 #define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
                (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
-#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#define CFG_RESET_VECTOR_ADDRESS 0xfffffffc
 #endif
 
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS    0xeffffffc
+#ifndef CFG_RESET_VECTOR_ADDRESS
+#define CFG_RESET_VECTOR_ADDRESS       0xeffffffc
 #endif
 
 /*
index 01a9f43cbaeb455e3e125e87f825f314287c64b1..506f1b7e268bb5accb40ed724a326ae23865f67d 100644 (file)
 
 #ifdef CONFIG_RAMBOOT_PBL
 #ifndef CONFIG_SDCARD
-#define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
+#define CFG_RESET_VECTOR_ADDRESS     0xfffffffc
 #else
 #define RESET_VECTOR_OFFSET            0x27FFC
 #define BOOT_PAGE_OFFSET               0x27000
 
 #ifdef CONFIG_SDCARD
-#define CONFIG_RESET_VECTOR_ADDRESS    0x200FFC
+#define CFG_RESET_VECTOR_ADDRESS       0x200FFC
 #define CFG_SYS_MMC_U_BOOT_SIZE        (768 << 10)
 #define CFG_SYS_MMC_U_BOOT_DST 0x00200000
 #define CFG_SYS_MMC_U_BOOT_START       0x00200000
@@ -34,8 +34,8 @@
 
 /* High Level Configuration Options */
 
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS    0xeffffffc
+#ifndef CFG_RESET_VECTOR_ADDRESS
+#define CFG_RESET_VECTOR_ADDRESS       0xeffffffc
 #endif
 
 #define CFG_SYS_NUM_CPC                CONFIG_SYS_NUM_DDR_CTLRS
index 33ee23ece1d14d2a900a5da68b8aebd55b74c229..58dff495ac5fe10eb606a2526f6dbc9a0a562e95 100644 (file)
 
 /* High Level Configuration Options */
 
-#define CONFIG_RESET_VECTOR_ADDRESS    0xebfffffc
+#define CFG_RESET_VECTOR_ADDRESS       0xebfffffc
 
 #define CFG_SYS_NUM_CPC                CONFIG_SYS_NUM_DDR_CTLRS
 
index 41e7f53bd57ee157e67725e2eba9d4aee09113e3..832ad9c3ece0bb33d5604e6211ef763c02e299fd 100644 (file)
 #endif /* not CONFIG_TPL_BUILD */
 #endif
 
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS    0xeffffffc
+#ifndef CFG_RESET_VECTOR_ADDRESS
+#define CFG_RESET_VECTOR_ADDRESS       0xeffffffc
 #endif
 
 #define CFG_SYS_CCSRBAR                0xffe00000