i2c: rcar_i2c: Add comments about registers & values

Document the meaning of macros related to registers and values to be
written to them.

Signed-off-by: Ismael Luceno <ismael.luceno@silicon-gears.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>

diff --git a/drivers/i2c/rcar_i2c.c b/drivers/i2c/rcar_i2c.c
index a57f72a228f1b77d600d71aeb55d2a27ad2b3986..d7b27204cb2d9e03bd32811d3c472fc635e6f3d7 100644 (file)
--- a/drivers/i2c/rcar_i2c.c
+++ b/drivers/i2c/rcar_i2c.c
@@ -18,35 +18,40 @@
 #include <asm/io.h>
 #include <wait_bit.h>
 
-#define RCAR_I2C_ICSCR                 0x00
-#define RCAR_I2C_ICMCR                 0x04
-#define RCAR_I2C_ICMCR_MDBS            BIT(7)
-#define RCAR_I2C_ICMCR_FSCL            BIT(6)
-#define RCAR_I2C_ICMCR_FSDA            BIT(5)
-#define RCAR_I2C_ICMCR_OBPC            BIT(4)
-#define RCAR_I2C_ICMCR_MIE             BIT(3)
+#define RCAR_I2C_ICSCR                 0x00 /* slave ctrl */
+#define RCAR_I2C_ICMCR                 0x04 /* master ctrl */
+#define RCAR_I2C_ICMCR_MDBS            BIT(7) /* non-fifo mode switch */
+#define RCAR_I2C_ICMCR_FSCL            BIT(6) /* override SCL pin */
+#define RCAR_I2C_ICMCR_FSDA            BIT(5) /* override SDA pin */
+#define RCAR_I2C_ICMCR_OBPC            BIT(4) /* override pins */
+#define RCAR_I2C_ICMCR_MIE             BIT(3) /* master if enable */
 #define RCAR_I2C_ICMCR_TSBE            BIT(2)
-#define RCAR_I2C_ICMCR_FSB             BIT(1)
-#define RCAR_I2C_ICMCR_ESG             BIT(0)
-#define RCAR_I2C_ICSSR                 0x08
-#define RCAR_I2C_ICMSR                 0x0c
+#define RCAR_I2C_ICMCR_FSB             BIT(1) /* force stop bit */
+#define RCAR_I2C_ICMCR_ESG             BIT(0) /* enable start bit gen */
+#define RCAR_I2C_ICSSR                 0x08 /* slave status */
+#define RCAR_I2C_ICMSR                 0x0c /* master status */
 #define RCAR_I2C_ICMSR_MASK            0x7f
-#define RCAR_I2C_ICMSR_MNR             BIT(6)
-#define RCAR_I2C_ICMSR_MAL             BIT(5)
-#define RCAR_I2C_ICMSR_MST             BIT(4)
+#define RCAR_I2C_ICMSR_MNR             BIT(6) /* Nack */
+#define RCAR_I2C_ICMSR_MAL             BIT(5) /* Arbitration lost */
+#define RCAR_I2C_ICMSR_MST             BIT(4) /* Stop */
 #define RCAR_I2C_ICMSR_MDE             BIT(3)
 #define RCAR_I2C_ICMSR_MDT             BIT(2)
 #define RCAR_I2C_ICMSR_MDR             BIT(1)
 #define RCAR_I2C_ICMSR_MAT             BIT(0)
-#define RCAR_I2C_ICSIER                        0x10
-#define RCAR_I2C_ICMIER                        0x14
-#define RCAR_I2C_ICCCR                 0x18
+#define RCAR_I2C_ICSIER                        0x10 /* slave irq enable */
+#define RCAR_I2C_ICMIER                        0x14 /* master irq enable */
+#define RCAR_I2C_ICCCR                 0x18 /* clock dividers */
 #define RCAR_I2C_ICCCR_SCGD_OFF                3
-#define RCAR_I2C_ICSAR                 0x1c
-#define RCAR_I2C_ICMAR                 0x20
-#define RCAR_I2C_ICRXD_ICTXD           0x24
+#define RCAR_I2C_ICSAR                 0x1c /* slave address */
+#define RCAR_I2C_ICMAR                 0x20 /* master address */
+#define RCAR_I2C_ICRXD_ICTXD           0x24 /* data port */
+/*
+ * First Bit Setup Cycle (Gen3).
+ * Defines 1st bit delay between SDA and SCL.
+ */
 #define RCAR_I2C_ICFBSCR               0x38
-#define RCAR_I2C_ICFBSCR_TCYC17                0x0f
+#define RCAR_I2C_ICFBSCR_TCYC17                0x0f /* 17*Tcyc */
+
 
 enum rcar_i2c_type {
        RCAR_I2C_TYPE_GEN2,