riscv: Align the trap handler to 64 bytes

This is required on CPUs which always operate in CLIC mode, such as the
T-HEAD E906 and E907. Per the CLIC specification: "In this mode, the
trap vector base address held in mtvec is constrained to be aligned on a
64-byte or larger power-of-two boundary."

Reported-by: Madushan Nishantha <jlmadushan@gmail.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

diff --git a/arch/riscv/cpu/mtrap.S b/arch/riscv/cpu/mtrap.S
index 6eb3ed1d5a8838c1d58aedfa317cefb324f9cabc..5cad7b41ff76ec14bda87e640e60532fbff29fce 100644 (file)
--- a/arch/riscv/cpu/mtrap.S
+++ b/arch/riscv/cpu/mtrap.S
@@ -26,7 +26,7 @@
        .text
 
        /* trap entry */
-       .align 2
+       .align 6
        .global trap_entry
 trap_entry:
        addi sp, sp, -32 * REGBYTES