clock-frequency = <25000000>;
};
-&dmsc {
- k3_sysreset: sysreset-controller {
- compatible = "ti,sci-sysreset";
- bootph-all;
- };
-};
-
&sd_pins_default {
/* Force to use SDCD card detect pin */
pinctrl-single,pins = <
bootph-all;
};
-&dmsc {
- k3_sysreset: sysreset-controller {
- compatible = "ti,sci-sysreset";
- bootph-all;
- };
-};
-
&fss {
bootph-all;
};
bootph-all;
};
-&dmsc {
- k3_sysreset: sysreset-controller {
- compatible = "ti,sci-sysreset";
- bootph-all;
- };
-};
-
&fss {
bootph-all;
};
&dmsc {
bootph-all;
- k3_sysreset: sysreset-controller {
- compatible = "ti,sci-sysreset";
- bootph-all;
- };
};
&vdd_mmc1 {
&dmsc {
bootph-pre-ram;
-
- k3_sysreset: sysreset-controller {
- compatible = "ti,sci-sysreset";
- bootph-pre-ram;
- };
};
bootph-all;
};
-&dmsc {
- k3_sysreset: sysreset-controller {
- compatible = "ti,sci-sysreset";
- bootph-all;
- };
-};
-
&sdhci0 {
bootph-all;
};
&dmsc {
bootph-all;
- k3_sysreset: sysreset-controller {
- compatible = "ti,sci-sysreset";
- bootph-all;
- };
};
&dmss {
clock-frequency = <200000000>;
};
-&dmsc {
- k3_sysreset: sysreset-controller {
- compatible = "ti,sci-sysreset";
- bootph-all;
- };
-};
-
&sdhci0 {
status = "disabled";
};
&dmsc {
bootph-all;
- k3_sysreset: sysreset-controller {
- compatible = "ti,sci-sysreset";
- bootph-all;
- };
};
&k3_pds {
&sms {
bootph-all;
- k3_sysreset: sysreset-controller {
- compatible = "ti,sci-sysreset";
- bootph-all;
- };
};
&main_pmx0 {
bootph-pre-ram;
};
-&sms {
- k3_sysreset: sysreset-controller {
- compatible = "ti,sci-sysreset";
- bootph-pre-ram;
- };
-};
-
#ifdef CONFIG_TARGET_J784S4_A72_EVM
#define SPL_AM69_SK_DTB "spl/dts/ti/k3-am69-sk.dtb"
&dmsc {
bootph-all;
- k3_sysreset: sysreset-controller {
- compatible = "ti,sci-sysreset";
- bootph-all;
- };
};
&k3_pds {
&dmsc {
bootph-all;
- k3_sysreset: sysreset-controller {
- compatible = "ti,sci-sysreset";
- bootph-all;
- };
};
&k3_pds {
&dmsc {
bootph-all;
- k3_sysreset: sysreset-controller {
- compatible = "ti,sci-sysreset";
- bootph-all;
- };
};
&k3_pds {
&dmsc {
bootph-all;
- k3_sysreset: sysreset-controller {
- compatible = "ti,sci-sysreset";
- bootph-all;
- };
};
&k3_pds {
&sms {
bootph-all;
- k3_sysreset: sysreset-controller {
- compatible = "ti,sci-sysreset";
- bootph-all;
- };
};
&main_pmx0 {
"tchanrt", "rflow";
bootph-pre-ram;
};
-
-&sms {
- k3_sysreset: sysreset-controller {
- compatible = "ti,sci-sysreset";
- bootph-pre-ram;
- };
-};
+++ /dev/null
-Texas Instruments TI SCI System Reset Controller
-================================================
-
-Some TI SoCs contain a system controller (like the SYSFW, etc...) that is
-responsible for controlling the state of the IPs that are present.
-Communication between the host processor running an OS and the system
-controller happens through a protocol known as TI SCI [1].
-
-[1] http://processors.wiki.ti.com/index.php/TISCI
-
-System Reset Controller Node
-============================
-The sysreset controller node represents the reset for the overall SoC
-which is managed by the SYSFW. Because this relies on the TI SCI protocol
-to communicate with the SYSFW it must be a child of the sysfw node.
-
-Required Properties:
---------------------
- - compatible: Must be "ti,sci-sysreset"
-
-Example (AM65x):
-----------------
- sysfw: sysfw {
- compatible = "ti,am654-system-controller";
- ...
- k3_sysreset: sysreset-controller {
- compatible = "ti,sci-sysreset";
- };
- };