]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
spi: Zap CONFIG_HARD_SPI
authorJagan Teki <jagan@amarulasolutions.com>
Sat, 24 Nov 2018 09:01:12 +0000 (14:31 +0530)
committerJagan Teki <jagan@amarulasolutions.com>
Tue, 27 Nov 2018 15:36:53 +0000 (21:06 +0530)
In legacy CONFIG_HARD_SPI initalizing spi_init code, which
was removed during dm conversion cleanup.

So remove the dead instances of CONFIG_HARD_SPI, and related
code.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
23 files changed:
README
arch/powerpc/include/asm/config.h
board/freescale/mpc8349emds/mpc8349emds.c
board/ids/ids8313/ids8313.c
common/board_f.c
include/configs/M52277EVB.h
include/configs/M54418TWR.h
include/configs/M54451EVB.h
include/configs/M54455EVB.h
include/configs/MPC8536DS.h
include/configs/P1022DS.h
include/configs/UCP1020.h
include/configs/controlcenterd.h
include/configs/dreamplug.h
include/configs/ds109.h
include/configs/ids8313.h
include/configs/mx31pdk.h
include/configs/mxs.h
include/configs/p1_p2_rdb_pc.h
include/configs/p1_twr.h
include/configs/stmark2.h
include/configs/ts4800.h
scripts/config_whitelist.txt

diff --git a/README b/README
index a46c7c63a4fed72b16cfbaeb2620e9c1e196b396..17d56b80349a7a97e847e30ab197e768e502b268 100644 (file)
--- a/README
+++ b/README
@@ -1932,14 +1932,6 @@ The following options need to be configured:
                SPI configuration items (port pins to use, etc). For
                an example, see include/configs/sacsng.h.
 
-               CONFIG_HARD_SPI
-
-               Enables a hardware SPI driver for general-purpose reads
-               and writes.  As with CONFIG_SOFT_SPI, the board configuration
-               must define a list of chip-select function pointers.
-               Currently supported on some MPC8xxx processors.  For an
-               example, see include/configs/mpc8349emds.h.
-
                CONFIG_SYS_SPI_MXC_WAIT
                Timeout for waiting until spi transfer completed.
                default: (CONFIG_SYS_HZ/100)     /* 10 ms */
index 849a69acedcdc02d301d0aa2487cb6878a1865f5..c9c99646309e6bfba09b0d6d823de37c0d3c51b7 100644 (file)
   #define HWCONFIG_BUFFER_SIZE 256
 #endif
 
-/* CONFIG_HARD_SPI triggers SPI bus initialization in PowerPC */
-#if defined(CONFIG_MPC8XXX_SPI) || defined(CONFIG_FSL_ESPI)
-# ifndef CONFIG_HARD_SPI
-#  define CONFIG_HARD_SPI
-# endif
-#endif
-
 #define CONFIG_LMB
 #define CONFIG_SYS_BOOT_RAMDISK_HIGH
 
index 4ec0af4d1c5618ada62056792d246219fe591ac4..d40ed3742e02f251c24d18dec93b802d16f072d9 100644 (file)
@@ -273,7 +273,7 @@ void spi_cs_deactivate(struct spi_slave *slave)
 
        iopd->dat |=  SPI_CS_MASK;
 }
-#endif /* CONFIG_HARD_SPI */
+#endif
 
 #if defined(CONFIG_OF_BOARD_SETUP)
 int ft_board_setup(void *blob, bd_t *bd)
index a411d4e7f6fd2fb65b7d72366851ca5265bec33e..d547af4b05acfc28438aacb8ff82f33cd79e99f0 100644 (file)
@@ -208,4 +208,4 @@ void spi_cs_deactivate(struct spi_slave *slave)
        /* deactivate the spi_cs */
        setbits_be32(&iopd->dat, IDSCPLD_SPI_CS_MASK);
 }
-#endif /* CONFIG_HARD_SPI */
+#endif
index 60634e52cd7140e6bd8d01a64984bb585bd4c62a..a3e80ca9512f79667ea416515b03cd374c6706c2 100644 (file)
@@ -257,15 +257,6 @@ __weak int init_func_vid(void)
 }
 #endif
 
-#if defined(CONFIG_HARD_SPI)
-static int init_func_spi(void)
-{
-       puts("SPI:   ");
-       puts("ready\n");
-       return 0;
-}
-#endif
-
 static int setup_mon_len(void)
 {
 #if defined(__ARM__) || defined(__MICROBLAZE__)
@@ -863,9 +854,6 @@ static const init_fnc_t init_sequence_f[] = {
 #endif
 #if defined(CONFIG_VID) && !defined(CONFIG_SPL)
        init_func_vid,
-#endif
-#if defined(CONFIG_HARD_SPI)
-       init_func_spi,
 #endif
        announce_dram_init,
        dram_init,              /* configure available RAM banks */
index 11cb3955da5fe444746e34d7a1836bc99a1d99f7..83d774527adcfc6ad39d621990d31a98f3da1925 100644 (file)
 
 /* DSPI and Serial Flash */
 #define CONFIG_CF_DSPI
-#define CONFIG_HARD_SPI
 #define CONFIG_SYS_SBFHDR_SIZE         0x7
 #ifdef CONFIG_CMD_SPI
 #      define CONFIG_SYS_DSPI_CS2
index f08896ef0a05108819640504b9aae0c5b072ab8a..4b8ef38c0befc7fb6b3cc4d31515fb474b45adcf 100644 (file)
 /* DSPI and Serial Flash */
 #define CONFIG_CF_DSPI
 #define CONFIG_SERIAL_FLASH
-#define CONFIG_HARD_SPI
 #define CONFIG_SYS_SBFHDR_SIZE         0x7
 #ifdef CONFIG_CMD_SPI
 
index 16becbdbedd81e3051d908adbb12d6206fcd3e0a..87cdbae1dbf56e0ffdc5a54abec1fa89c8660143 100644 (file)
 /* DSPI and Serial Flash */
 #define CONFIG_CF_DSPI
 #define CONFIG_SERIAL_FLASH
-#define CONFIG_HARD_SPI
 #define CONFIG_SYS_SBFHDR_SIZE         0x7
 #ifdef CONFIG_CMD_SPI
 
index 99b60d5d82301d159f06a2071f9bd02247716097..d41b7c4492953de1e382da7f7ea3b3184a91ba95 100644 (file)
 
 /* DSPI and Serial Flash */
 #define CONFIG_CF_DSPI
-#define CONFIG_HARD_SPI
 #define CONFIG_SYS_SBFHDR_SIZE         0x13
 #ifdef CONFIG_CMD_SPI
 
index 524a10fc95a8b0b0151e05c15d0c42f391233a1d..86a1233e322014416c118b96ec5073000c55695c 100644 (file)
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 #define CONFIG_SYS_EEPROM_BUS_NUM      1
 
-/*
- * eSPI - Enhanced SPI
- */
-#define CONFIG_HARD_SPI
-
 #if defined(CONFIG_SPI_FLASH)
 #define CONFIG_SF_DEFAULT_SPEED        10000000
 #define CONFIG_SF_DEFAULT_MODE 0
index c9ed70ca4cb9761445bb215065d3c91cd54be2ee..eeb19a9fa68a7399b2ed091181deefc0a4f0092e 100644 (file)
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 #define CONFIG_SYS_EEPROM_BUS_NUM      1
 
-/*
- * eSPI - Enhanced SPI
- */
-
-#define CONFIG_HARD_SPI
-
 #define CONFIG_SF_DEFAULT_SPEED                10000000
 #define CONFIG_SF_DEFAULT_MODE         0
 
index 423ecd71c279c17a9f221482fde72033f20c522d..1bbe9d9b375755dd6c15c17b7372eaa336ef3706 100644 (file)
 #define CONFIG_SYS_I2C_NCT72_ADDR      0x4C
 #define CONFIG_SYS_I2C_IDT6V49205B     0x69
 
-/*
- * eSPI - Enhanced SPI
- */
-#define CONFIG_HARD_SPI
-
 #define CONFIG_SF_DEFAULT_SPEED                10000000
 #define CONFIG_SF_DEFAULT_MODE         SPI_MODE_0
 
index 4adcd956efb709682a5351c6124988d0c9eeb8cf..1908d35bcc698e59a964c8f49aaa9f7d088a2ae8 100644 (file)
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
 
 #ifndef CONFIG_TRAILBLAZER
-/*
- * eSPI - Enhanced SPI
- */
-#define CONFIG_HARD_SPI
 
 #define CONFIG_SF_DEFAULT_SPEED                10000000
 #define CONFIG_SF_DEFAULT_MODE         0
index 1c94bf9fa1bf9eb5ae4a183eb42c0b2c2fee4675..f4d717213ce172ecab751d88387864d99a81d86e 100644 (file)
@@ -35,7 +35,6 @@
 #endif
 
 #ifdef CONFIG_CMD_SF
-#define CONFIG_HARD_SPI                        1
 #define CONFIG_ENV_SPI_BUS             0
 #define CONFIG_ENV_SPI_CS              0
 #define CONFIG_ENV_SPI_MAX_HZ          50000000 /* 50 MHz */
index c06f0058deb57381609aeca016536d07ff774280..2c7928e88c1c181b80f53921cc0588c5b6b1f7b3 100644 (file)
@@ -38,7 +38,6 @@
 #endif
 
 #ifdef CONFIG_CMD_SF
-#define CONFIG_HARD_SPI                        1
 #define CONFIG_ENV_SPI_BUS             0
 #define CONFIG_ENV_SPI_CS              0
 #define CONFIG_ENV_SPI_MAX_HZ          50000000 /* 50 MHz */
index 28124dd4b12efe602cfb4f02f162a01531203bd1..7e4c497fe0ae65b22dd5a3f02d61c1593cccdf63 100644 (file)
  */
 #define CONFIG_TSEC1
 #define CONFIG_TSEC2
-#define CONFIG_HARD_SPI
 
 /*
  * NOR FLASH setup
 #define CONFIG_RTC_PCF8563
 #define CONFIG_SYS_I2C_RTC_ADDR        0x51
 
-/*
- * SPI setup
- */
-#ifdef CONFIG_HARD_SPI
-#define CONFIG_SYS_GPIO1_PRELIM
-#define CONFIG_SYS_GPIO1_DIR           0x00000001
-#define CONFIG_SYS_GPIO1_DAT           0x00000001
-#endif
-
 /*
  * Ethernet setup
  */
index 7d84d160b4c3d4e7b04a0629027414b7beb6c84b..4765764f83a9edebf8e38ef9d26e9aeffc81fcb9 100644 (file)
@@ -43,7 +43,6 @@
 #define CONFIG_MXC_UART
 #define CONFIG_MXC_UART_BASE   UART1_BASE
 
-#define CONFIG_HARD_SPI
 #define CONFIG_DEFAULT_SPI_BUS 1
 #define CONFIG_DEFAULT_SPI_MODE        (SPI_MODE_0 | SPI_CS_HIGH)
 
index 9e59e7a4dcb3996089b23117a211e62aa262d998..4bb3621a42860d6112dd0f5ce9e86849608e27e4 100644 (file)
 
 /* SPI */
 #ifdef CONFIG_CMD_SPI
-#define CONFIG_HARD_SPI
 #define CONFIG_SPI_HALF_DUPLEX
 #endif
 
index 9465fb47027b141decdfc6eddd1a0632346c1584..459ecf328f20853ab0b46c78cef8ac08527b9c81 100644 (file)
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 
-/*
- * eSPI - Enhanced SPI
- */
-#define CONFIG_HARD_SPI
-
 #if defined(CONFIG_SPI_FLASH)
 #define CONFIG_SF_DEFAULT_SPEED        10000000
 #define CONFIG_SF_DEFAULT_MODE 0
index d018c22afdb2908bf4fa03f77d606f8ad93bdc32..4f48370648807e11024dc08a0e8584a204a43a9a 100644 (file)
@@ -214,11 +214,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 
-/*
- * eSPI - Enhanced SPI
- */
-#define CONFIG_HARD_SPI
-
 #if defined(CONFIG_PCI)
 /*
  * General PCI
index c408db865ebddf37f83b13d7d0de679907cf8ac2..33ddc67bf4a34e7051a3f32268875168765e7981 100644 (file)
@@ -66,7 +66,6 @@
 #define CONFIG_CF_DSPI
 #define CONFIG_SF_DEFAULT_SPEED                50000000
 #define CONFIG_SERIAL_FLASH
-#define CONFIG_HARD_SPI
 #define CONFIG_ENV_SPI_BUS             0
 #define CONFIG_ENV_SPI_CS              1
 
index 956f7795f1f525cbbf12b6004b02358b689a6e03..4e274bd4141d1151dc7c1d3e061cb6be75681380 100644 (file)
 #define CONFIG_MXC_UART
 #define CONFIG_MXC_UART_BASE   UART1_BASE
 
-/*
- * SPI Configs
- * */
-#define CONFIG_HARD_SPI /* puts SPI: ready */
-
 /*
  * MMC Configs
  * */
index abfb0ff89fa988f5f65a44b9ff6a313ae43df0c2..1404fd855bf31c96449edc6c7e9845d53be7ff82 100644 (file)
@@ -750,7 +750,6 @@ CONFIG_G_DNL_UMS_PRODUCT_NUM
 CONFIG_G_DNL_UMS_VENDOR_NUM
 CONFIG_H264_FREQ
 CONFIG_H8300
-CONFIG_HARD_SPI
 CONFIG_HAS_ETH0
 CONFIG_HAS_ETH1
 CONFIG_HAS_ETH2