MIPS: Enable use of the instruction cache earlier

Enable use of the instruction cache immediately after it has been
initialised. This will only take effect if U-Boot was linked to run from
kseg0 rather than kseg1, but when this is the case the data cache
initialisation code will run cached & thus significantly faster.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>

diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S
index fc6dd66aa655b9e1c7a8b25c5311e96e0ff6f4cb..827a544987852587a1ca7018e2a160c4b71b19ca 100644 (file)
--- a/arch/mips/cpu/start.S
+++ b/arch/mips/cpu/start.S
@@ -12,10 +12,6 @@
 #include <asm/regdef.h>
 #include <asm/mipsregs.h>
 
-#ifndef CONFIG_SYS_MIPS_CACHE_MODE
-#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
-#endif
-
 #ifndef CONFIG_SYS_INIT_SP_ADDR
 #define CONFIG_SYS_INIT_SP_ADDR        (CONFIG_SYS_SDRAM_BASE + \
                                CONFIG_SYS_INIT_SP_OFFSET)
@@ -154,10 +150,6 @@ reset:
        PTR_LA  t9, mips_cache_reset
        jalr    t9
         nop
-
-       /* ... and enable them */
-       li      t0, CONFIG_SYS_MIPS_CACHE_MODE
-       mtc0    t0, CP0_CONFIG
 #endif
 
        /* Set up temporary stack */

diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S
index bc8ab27b58d92289088b8659d0ac224babdb6d46..974dfe9cea3ce0bb4613a0337638f45860b4b5f4 100644 (file)
--- a/arch/mips/lib/cache_init.S
+++ b/arch/mips/lib/cache_init.S
@@ -172,6 +172,19 @@ LEAF(mips_cache_reset)
        cache_loop      t0, t1, t8, INDEX_STORE_TAG_I
 #endif
 
+       /* Enable use of the I-cache by setting Config.K0 */
+       sync
+       mfc0            t0, CP0_CONFIG
+       li              t1, CONFIG_SYS_MIPS_CACHE_MODE
+#if __mips_isa_rev >= 2
+       ins             t0, t1, 0, 3
+#else
+       ori             t0, t0, CONF_CM_CMASK
+       xori            t0, t0, CONF_CM_CMASK
+       or              t0, t0, t1
+#endif
+       mtc0            t0, CP0_CONFIG
+
        /*
         * then initialize D-cache.
         */