riscv: sifive: dts: fu540: set ethernet clock rate

Set ethernet clock rate to 125 Mhz so that it will work with 1000Mbps,
Earlier this is done by FSBL. With this change We can remove the
ethernet clock rate code from FSBL.

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi
index fc91a7c987fd4eb296f6968c4c413b4a34916d46..9bba554f9d1b6a69164b2e27e7995a0249e47f81 100644 (file)
--- a/arch/riscv/dts/fu540-c000-u-boot.dtsi
+++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
@@ -82,3 +82,8 @@
 &qspi2 {
        u-boot,dm-spl;
 };
+
+&eth0 {
+       assigned-clocks = <&prci PRCI_CLK_GEMGXLPLL>;
+       assigned-clock-rates = <125000000>;
+};