such as ARM architectural timer initialization.
- Linux Kernel Interface:
- CONFIG_MEMSIZE_IN_BYTES [relevant for MIPS only]
-
- When transferring memsize parameter to Linux, some versions
- expect it to be in bytes, others in MB.
- Define CONFIG_MEMSIZE_IN_BYTES to make it in bytes.
-
CONFIG_OF_LIBFDT
New kernel versions are expecting firmware settings to be
Support for generic parallel port TPM devices. Only one device
per system is supported at this time.
- CONFIG_TPM_TIS_BASE_ADDRESS
- Base address where the generic TPM device is mapped
- to. Contemporary x86 systems usually map it at
- 0xfed40000.
-
CONFIG_TPM
Define this to enable the TPM support library which provides
functional interfaces to some TPM commands.
/* SATA */
#define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000)
#ifdef CONFIG_DDR_SPD
-#define CONFIG_VERY_BIG_RAM
#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30)
#endif
/* Needed for SPI NOR booting in SPL */
#define CONFIG_DM_SEQ_ALIAS 1
-/*
- * I2C related stuff
- */
-#ifdef CONFIG_CMD_I2C
-#ifndef CONFIG_SYS_I2C_SOFT
-#define CONFIG_I2C_MVTWSI
-#endif
-#endif
-
#endif /* __MVEBU_CONFIG_H */
#define CFG_SYS_FM_MURAM_SIZE 0x60000
#ifdef CONFIG_ARCH_B4860
-#define CONFIG_NUM_DSP_CPUS 6
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
#define CFG_SYS_NUM_FM1_DTSEC 6
#define CFG_SYS_NUM_FM1_10GEC 2
* restricting used physical memory to the first 128MB.
*/
#if XCHAL_HAVE_PTP_MMU
-#define CONFIG_VERY_BIG_RAM
#define CONFIG_MAX_MEM_MAPPED (128 << 20)
#endif
/* reset the phy */
miiphy_reset(name, devadr);
- printf(PHY_NO" Initialized on %s\n", name);
+ printf("Initialized on %s\n", name);
}
void reset_phy(void)
DECLARE_GLOBAL_DATA_PTR;
-#ifndef CONFIG_MVGBE_PORTS
-# define CONFIG_MVGBE_PORTS {0, 0}
-#endif
-
#define MV_PHY_ADR_REQUEST 0xee
#define MVGBE_SMI_REG (((struct mvgbe_registers *)MVGBE0_BASE)->smi)
#define MVGBE_PGADR_REG 22
#ifndef __MVGBE_H__
#define __MVGBE_H__
-/* PHY_BASE_ADR is board specific and can be configured */
-#if defined (CONFIG_PHY_BASE_ADR)
-#define PHY_BASE_ADR CONFIG_PHY_BASE_ADR
-#else
-#define PHY_BASE_ADR 0x08 /* default phy base addr */
-#endif
-
/* Constants */
#define INT_CAUSE_UNMASK_ALL 0x0007ffff
#define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff
phys_size_t get_effective_memsize(void)
{
- if (!IS_ENABLED(CONFIG_VERY_BIG_RAM))
- return gd->ram_size;
-
- /* Limit stack to what we can reasonable map */
- return ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ?
- CONFIG_MAX_MEM_MAPPED : gd->ram_size);
+ return gd->ram_size;
}
/**
* Environment Configuration
*/
-#define CONFIG_NETDEV "eth1"
-
-#define CONFIG_FDTFILE "mpc8379_rdb.dtb"
+#define FDTFILE "mpc8379_rdb.dtb"
#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=" CONFIG_NETDEV "\0" \
+ "netdev=eth1\0" \
"uboot=" CONFIG_UBOOTPATH "\0" \
"tftpflash=tftp $loadaddr $uboot;" \
"protect off " __stringify(CONFIG_TEXT_BASE) \
"cmp.b $loadaddr " __stringify(CONFIG_TEXT_BASE) \
" $filesize\0" \
"fdtaddr=780000\0" \
- "fdtfile=" CONFIG_FDTFILE "\0" \
+ "fdtfile=" FDTFILE "\0" \
"ramdiskaddr=1000000\0" \
"ramdiskfile=rootfs.ext2.gz.uboot\0" \
"console=ttyS0\0" \
#ifdef CONFIG_SPIFLASH
#ifdef CONFIG_NXP_ESBC
-#define CONFIG_RAMBOOT_SPIFLASH
#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
#else
#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10)
#define __CONFIG_H
#ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#endif
/*
* Config the L3 Cache as L3 SRAM
*/
-#define CFG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
+#define CFG_SYS_INIT_L3_ADDR CONFIG_TEXT_BASE
#ifdef CONFIG_PHYS_64BIT
-#define CFG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
- CONFIG_RAMBOOT_TEXT_BASE)
+#define CFG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_TEXT_BASE)
#else
#define CFG_SYS_INIT_L3_ADDR_PHYS CFG_SYS_INIT_L3_ADDR
#endif
/*
* DDR Setup
*/
-#define CONFIG_VERY_BIG_RAM
#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
#endif
-#define CONFIG_FSL_CPLD
#define CPLD_BASE 0xffdf0000 /* CPLD registers */
#ifdef CONFIG_PHYS_64BIT
#define CPLD_BASE_PHYS 0xfffdf0000ull
#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS + 0x8000000}
/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
#define CFG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
#ifdef CONFIG_PHYS_64BIT
#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
/* size in bytes reserved for initial data */
#include <asm/arch/config.h>
-/* There is no PHY directly connected so don't ask it for link status */
-
-/*
- * Ethernet Driver configuration
- */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_MVGBE_PORTS {1, 0} /* enable a single port */
-#define CONFIG_PHY_BASE_ADR 0x01
-#endif /* CONFIG_CMD_NET */
#endif /* _CONFIG_SBX81LIFKW_H */
/* size in bytes reserved for initial data */
#include <asm/arch/config.h>
-/* There is no PHY directly connected so don't ask it for link status */
-
-/*
- * Ethernet Driver configuration
- */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_MVGBE_PORTS {1, 0} /* enable a single port */
-#define CONFIG_PHY_BASE_ADR 0x01
-#endif /* CONFIG_CMD_NET */
#endif /* _CONFIG_SBX81LIFXCAT_H */
/*
* DDR Setup
*/
-#define CONFIG_VERY_BIG_RAM
#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#if defined(CONFIG_TARGET_T1024RDB)
#endif
/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
#ifdef CONFIG_PHYS_64BIT
#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
/*
* DDR Setup
*/
-#define CONFIG_VERY_BIG_RAM
#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#endif
/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
*/
#define CFG_SYS_I2C_RTC_ADDR 0x68
-/*DVI encoder*/
-#define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75
#endif
/*
/*
* DDR Setup
*/
-#define CONFIG_VERY_BIG_RAM
#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#define CFG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
#endif
/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
/*
* DDR Setup
*/
-#define CONFIG_VERY_BIG_RAM
#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#define CFG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
#endif
/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
#ifdef CONFIG_RAMBOOT_PBL
#ifndef CONFIG_SDCARD
-#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#else
#define RESET_VECTOR_OFFSET 0x27FFC
/*
* DDR Setup
*/
-#define CONFIG_VERY_BIG_RAM
#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE)
/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024)
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
-/* FLASH */
-#define CONFIG_SPI_FLASH_QUAD
-
/* SH Ether */
#define CONFIG_SH_ETHER_USE_PORT 0
#define CONFIG_SH_ETHER_PHY_ADDR 0x1
*/
#define CFG_SYS_FLASH_BANKS_SIZES {0x4000000}
-/* max number of sectors on one chip */
-#define CONFIG_FLASH_SECTOR_SIZE (0x10000*2)
-
/* environments */
/* SPI FLASH */
#define CONFIG_TEGRA_ENABLE_UARTA
#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
-/* SPI */
-#define CONFIG_TEGRA_SLINK_CTRLS 6
-#define CONFIG_SPI_FLASH_SIZE (4 << 20)
-
#include "tegra-common-post.h"
#endif /* __CONFIG_H */
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
/* FLASH */
-#if !defined(CONFIG_MTD_NOR_FLASH)
-#define CONFIG_SH_QSPI_BASE 0xE6B10000
-#else
+#if defined(CONFIG_MTD_NOR_FLASH)
#define CFG_SYS_FLASH_BASE 0x00000000
#define CFG_SYS_FLASH_SIZE 0x04000000 /* 64 MB */
#define CFG_SYS_FLASH_BANKS_LIST { (CFG_SYS_FLASH_BASE) }
#define CONFIG_TEGRA_ENABLE_UARTA
#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
-/* SPI */
-#define CONFIG_TEGRA_SLINK_CTRLS 6
-#define CONFIG_SPI_FLASH_SIZE (4 << 20)
-
#include "tegra-common-post.h"
#endif /* __CONFIG_H */
#define CONFIG_TEGRA_ENABLE_UARTD
#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
-/* SPI */
-#define CONFIG_SPI_FLASH_SIZE (4 << 20)
-
#include "tegra-common-post.h"
#endif /* __CONFIG_H */
#include <asm/arch/imx-regs.h>
#include <linux/sizes.h>
-/* NAND support */
-
-#define CONFIG_FDTADDR 0x84000000
-
#define MEM_LAYOUT_ENV_SETTINGS \
"bootm_size=0x10000000\0" \
"fdt_addr_r=0x82000000\0" \
/* Environment in eMMC, at the end of 2nd "boot sector" */
-/* SPI */
-#define CONFIG_SPI_FLASH_SIZE (4 << 20)
-
#include "tegra-common-post.h"
#endif /* __CONFIG_H */
/* Remove or override few declarations from mv-common.h */
-/*
- * Ethernet Driver configuration
- */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
-#endif
-
/*
* Enable GPI0 support
*/
"initrd=/boot/uInitrd\0" \
"bootargs_root=ubi.mtd=1 root=ubi0:root rootfstype=ubifs ro\0"
-/*
- * Ethernet Driver configuration
- */
-#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
-#define CONFIG_PHY_BASE_ADR 0
-
#endif /* _CONFIG_DOCKSTAR_H */
#include <environment/ti/dfu.h>
-#define CONFIG_VERY_BIG_RAM
#define CONFIG_MAX_MEM_MAPPED 0x80000000
#ifndef CONFIG_QSPI_BOOT
"x_bootargs=console=ttyS0,115200\0" \
"x_bootargs_root=root=/dev/sda2 rootdelay=10\0"
-/*
- * Ethernet Driver configuration
- */
-#define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */
-#define CONFIG_PHY_BASE_ADR 0
-
#endif /* _CONFIG_DREAMPLUG_H */
"ipaddr=192.168.1.5\0" \
"usb0Mode=host\0"
-/*
- * Ethernet Driver configuration
- */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_MVGBE_PORTS {1, 0} /* enable one port */
-#define CONFIG_PHY_BASE_ADR 8
-#endif /* CONFIG_CMD_NET */
-
#endif /* _CONFIG_DS109_H */
#define CFG_SYS_DDRUA 0x05
#define CFG_SYS_PJPAR 0xFF
-/*-----------------------------------------------------------------------
- * I2C
- */
-
-#ifdef CONFIG_CMD_DATE
-#define CONFIG_I2C_RTC_ADDR 0x68
-#endif
-
#endif /* _CONFIG_M5282EVB_H */
/*---------------------------------------------------------------------*/
#include <configs/x86-common.h>
-#undef CONFIG_TPM_TIS_BASE_ADDRESS
-
#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \
"stdout=vidconsole\0" \
"stderr=vidconsole\0"
#if defined(CONFIG_ENV_IS_IN_MMC)
/* RiOTboard */
-#define CONFIG_FDTFILE "imx6dl-riotboard.dtb"
+#define FDTFILE "imx6dl-riotboard.dtb"
#define CFG_SYS_FSL_USDHC_NUM 3
#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
/* MarSBoard */
-#define CONFIG_FDTFILE "imx6q-marsboard.dtb"
+#define FDTFILE "imx6q-marsboard.dtb"
#define CFG_SYS_FSL_USDHC_NUM 2
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
CONSOLE_ENV_SETTINGS \
MEM_LAYOUT_ENV_SETTINGS \
- "fdtfile=" CONFIG_FDTFILE "\0" \
+ "fdtfile=" FDTFILE "\0" \
"finduuid=part uuid mmc 0:1 uuid\0" \
BOOTENV
/* Ethernet */
#define CONFIG_PHY_ID 0
-#define CONFIG_MACB_SEARCH_PHY
/* MMC */
#ifdef CONFIG_CMD_MMC
/* MMC SPL */
#define COPY_BL2_FNPTR_ADDR 0x02020030
-#define CONFIG_RD_LVL
-
#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE
#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
#define PHYS_SDRAM_2 (CFG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
#ifndef __CONFIG_EXYNOS5420_H
#define __CONFIG_EXYNOS5420_H
-#define CONFIG_VAR_SIZE_SPL
-
#define CONFIG_IRAM_TOP 0x02074000
#define CONFIG_PHY_IRAM_BASE 0x02020000
/* select serial console configuration */
-/* IRAM Layout */
-#define CONFIG_IRAM_BASE 0x02100000
-#define CONFIG_IRAM_SIZE 0x58000
-#define CONFIG_IRAM_END (CONFIG_IRAM_BASE + CONFIG_IRAM_SIZE)
#define CPU_RELEASE_ADDR secondary_boot_addr
/* select serial console configuration */
"kernel=/boot/uImage\0" \
"bootargs_root=ubi.mtd=root root=ubi0:root rootfstype=ubifs ro\0"
-/*
- * Ethernet Driver configuration
- */
-#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
-#define CONFIG_PHY_BASE_ADR 0
-
#endif /* _CONFIG_GOFLEXHOME_H */
"fdt=/boot/guruplug-server-plus.dtb\0" \
"bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs rw\0"
-/*
- * Ethernet Driver configuration
- */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */
-#define CONFIG_PHY_BASE_ADR 0
-#endif /* CONFIG_CMD_NET */
-
#endif /* _CONFIG_GURUPLUG_H */
"fdt=/boot/ib62x0.dtb\0" \
"bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs rw\0"
-/*
- * Ethernet driver configuration
- */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
-#define CONFIG_PHY_BASE_ADR 0
-#endif /* CONFIG_CMD_NET */
-
/*
* SATA driver configuration
*/
"kernel=/boot/uImage\0" \
"bootargs_root=noinitrd ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs\0"
-/*
- * Ethernet driver configuration
- *
- * This board has PCIe Wifi card, so allow Ethernet to be disabled
- */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
-#define CONFIG_PHY_BASE_ADR 11
-#endif /* CONFIG_CMD_NET */
-
#endif /* _CONFIG_ICONNECT_H */
#define CONFIG_TEGRA_ENABLE_UARTD
#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
-/* Environment in eMMC, at the end of 2nd "boot sector" */
-
-/* SPI */
-#define CONFIG_SPI_FLASH_SIZE (4 << 20)
-
#include "tegra-common-post.h"
#endif /* __CONFIG_H */
/* Network */
#define CONFIG_KSNET_NETCP_V1_5
#define CONFIG_KSNET_CPSW_NUM_PORTS 9
-#define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
#endif /* __CONFIG_K2E_EVM_H */
/* Network */
#define CONFIG_KSNET_NETCP_V1_5
#define CONFIG_KSNET_CPSW_NUM_PORTS 2
-#define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
#define PHY_ANEG_TIMEOUT 10000 /* PHY needs longer aneg time */
#define SPI_MTD_PARTS KEYSTONE_SPI1_MTD_PARTS
/* Network */
#define CONFIG_KSNET_NETCP_V1_5
#define CONFIG_KSNET_CPSW_NUM_PORTS 5
-#define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
#endif /* __CONFIG_K2L_EVM_H */
/*
* DDR Setup
*/
-#define CONFIG_VERY_BIG_RAM
#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
/* DDR */
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
-#define CONFIG_VERY_BIG_RAM
#define CFG_SYS_DDR_SDRAM_BASE 0x80000000
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
* Enable platform initialisation via misc_init_r() function
*/
-/*
- * Ethernet Driver configuration
- */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
-#endif
-
/*
* Enable GPI0 support
*/
* Linux Information
*/
#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
-#define CONFIG_SETUP_INITRD_TAG
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootenvfile=uEnv.txt\0" \
"fdtfile=da850-lego-ev3.dtb\0" \
/* Link Definitions */
-#define CONFIG_VERY_BIG_RAM
#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
/* Link Definitions */
-#define CONFIG_VERY_BIG_RAM
#define CFG_SYS_DDR_SDRAM_BASE 0x80000000
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#define CFG_SYS_NAND_FTIM3 0x0
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
-#define CONFIG_MTD_NAND_VERIFY_WRITE
#endif
#ifdef CONFIG_NAND_BOOT
#define CFG_SYS_NAND_FTIM3 0x0
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
-#define CONFIG_MTD_NAND_VERIFY_WRITE
#ifdef CONFIG_NAND_BOOT
#define CFG_SYS_NAND_U_BOOT_SIZE (1024 << 10)
/* Link Definitions */
-#define CONFIG_VERY_BIG_RAM
#define CFG_SYS_DDR_SDRAM_BASE 0x80000000
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#define CFG_SYS_NAND_FTIM3 0x0
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
-#define CONFIG_MTD_NAND_VERIFY_WRITE
/* IFC Timing Params */
#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
#define CFG_SYS_NAND_FTIM3 0x0
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
-#define CONFIG_MTD_NAND_VERIFY_WRITE
#endif
#ifdef CONFIG_NAND_BOOT
#define CFG_SYS_NAND_FTIM3 0x0
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
-#define CONFIG_MTD_NAND_VERIFY_WRITE
/*
* CPLD
/* Link Definitions */
#define CFG_SYS_FSL_QSPI_BASE 0x20000000
-#define CONFIG_VERY_BIG_RAM
#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#define CFG_SYS_NAND_FTIM3 0x0
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
-#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CFG_SYS_I2C_FPGA_ADDR 0x66
#define QIXIS_LBMAP_SWITCH 6
#define CFG_SYS_NAND_FTIM3 0x0
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
-#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CFG_SYS_I2C_FPGA_ADDR 0x66
#define QIXIS_BRDCFG4_OFFSET 0x54
/* Link Definitions */
-#define CONFIG_VERY_BIG_RAM
#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#define CFG_SYS_NAND_FTIM3 0x0
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
-#define CONFIG_MTD_NAND_VERIFY_WRITE
#define QIXIS_LBMAP_SWITCH 0x06
#define QIXIS_LBMAP_MASK 0x0f
#define CFG_SYS_NAND_FTIM3 0x0
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
-#define CONFIG_MTD_NAND_VERIFY_WRITE
#define QIXIS_LBMAP_SWITCH 0x06
#define QIXIS_LBMAP_MASK 0x0f
#define CFG_SYS_FLASH_BASE 0x20000000
/* DDR */
-#define CONFIG_VERY_BIG_RAM
#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
#define CFG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
*/
#define CONFIG_MALTA
-#define CONFIG_MEMSIZE_IN_BYTES
-
/*
* CPU Configuration
*/
#define CFG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_VERY_BIG_RAM
#define CONFIG_MAX_MEM_MAPPED 0x1c000000
#define CFG_SYS_INIT_SP_OFFSET 0x800000
/* Environment */
-/* Defines for SPL */
-
-#define CONFIG_SPI_ADDR 0x30000000
-#define CFG_SYS_UBOOT_BASE (CONFIG_SPI_ADDR + CONFIG_SPL_PAD_TO)
+#define CFG_SYS_UBOOT_BASE (0x30000000 + CONFIG_SPL_PAD_TO)
/* SPL -> Uboot */
#define CFG_SYS_NAND_BASE 0x60000000
#endif
-/* SPI */
-#ifdef CONFIG_CMD_SPI
-#define CONFIG_SPI_HALF_DUPLEX
-#endif
-
#endif /* __CONFIGS_MXS_H__ */
"bootargs=console=ttyS0,115200\0" \
"autostart=no\0"
-/*
- * Ethernet Driver configuration
- */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
-#define CONFIG_PHY_BASE_ADR 8
-#endif /* CONFIG_CMD_NET */
-
-/*
- * EFI partition
- */
-
#endif /* _CONFIG_NAS220_H */
#endif /* CONFIG_SPL_BUILD */
-/* Ethernet driver configuration */
-#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
-#define CONFIG_PHY_BASE_ADR 1
-
#endif /* _CONFIG_NSA310S_H */
#define CONFIG_TEGRA_ENABLE_UARTA
#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
-/* SPI */
-#define CONFIG_SPI_FLASH_SIZE (4 << 20)
-
#include "tegra-common-post.h"
#endif /* __CONFIG_H */
"x_bootcmd_usb=usb start\0" \
"x_bootargs_root=root=ubi0:rootfs rootfstype=ubifs\0"
-/*
- * Ethernet Driver configuration
- */
-#ifdef CONFIG_CMD_NET
-# ifdef CONFIG_BOARD_IS_OPENRD_BASE
-# define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
-# else
-# define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */
-# endif
-# ifdef CONFIG_BOARD_IS_OPENRD_ULTIMATE
-# define CONFIG_PHY_BASE_ADR 0x0
-# define PHY_NO "88E1121"
-# else
-# define CONFIG_PHY_BASE_ADR 0x8
-# define PHY_NO "88E1116"
-# endif
-#endif /* CONFIG_CMD_NET */
-
-/*
- * SATA Driver configuration
- */
-
#endif /* _CONFIG_OPENRD_BASE_H */
"bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
"source ${loadaddr}\0"
-/* MIU (Memory Interleaving Unit) */
-#define CONFIG_MIU_2BIT_21_7_INTERLEAVED
-
-#define RESERVE_BLOCK_SIZE (512)
-#define BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
-
#endif /* __CONFIG_H */
/* Environment in eMMC, at the end of 2nd "boot sector" */
-/* SPI */
-#define CONFIG_SPI_FLASH_SIZE (4 << 20)
-
#include "tegra-common-post.h"
#endif /* _P2371_0000_H */
/* Environment in eMMC, at the end of 2nd "boot sector" */
-/* SPI */
-#define CONFIG_SPI_FLASH_SIZE (4 << 20)
-
#include "tegra-common-post.h"
#endif /* _P2371_2180_H */
/* Environment in eMMC, at the end of 2nd "boot sector" */
-/* SPI */
-#define CONFIG_SPI_FLASH_SIZE (4 << 20)
-
#include "tegra-common-post.h"
#endif /* _P2571_H */
func(PXE, pxe, na) \
func(DHCP, dhcp, na)
-/* Environment at end of QSPI, in the VER partition */
-#define CONFIG_SPI_FLASH_SIZE (4 << 20)
-
#define BOARD_EXTRA_ENV_SETTINGS \
"preboot=if test -e mmc 1:1 /u-boot-preboot.scr; then " \
"load mmc 1:1 ${scriptaddr} /u-boot-preboot.scr; " \
/* PSRAM */
#define PHYS_PSRAM 0x70000000
#define PHYS_PSRAM_SIZE 0x00400000 /* 4MB */
-/* Slave EBI1, PSRAM connected */
-#define CONFIG_PSRAM_SCFG (AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY | \
- AT91_MATRIX_SCFG_FIXED_DEFMSTR(5) | \
- AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED | \
- AT91_MATRIX_SCFG_SLOT_CYCLE(255))
/* USB */
#define CFG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */
"bootcmd_usb=usb start; ext2load usb 0:1 0x00800000 /uImage; " \
"ext2load usb 0:1 0x01100000 /uInitrd\0"
-/*
- * Ethernet Driver configuration
- */
-#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
-#define CONFIG_PHY_BASE_ADR 0
-
#endif /* _CONFIG_POGO_E02_H */
BOOTENV
#endif /* CONFIG_SPL_BUILD */
-/*
- * Ethernet Driver configuration
- */
-#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
-#define CONFIG_PHY_BASE_ADR 0
-
#endif /* _CONFIG_POGO_V4_H */
#define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024)
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (1024u * 1024 * 1024)
-/* FLASH */
-#define CONFIG_SPI_FLASH_QUAD
-
/* SH Ether */
#define CONFIG_SH_ETHER_USE_PORT 0
#define CONFIG_SH_ETHER_PHY_ADDR 0x1
/*
* DDR Setup
*/
-#define CONFIG_VERY_BIG_RAM
#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#define DRAM_RSV_SIZE 0x08000000
#define CFG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE)
#define CFG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE)
-#define CONFIG_VERY_BIG_RAM
#define CONFIG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE)
/* ENV setting */
#define CONFIG_IRAM_BASE 0xff8c0000
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_TPL_BOOTROM_SUPPORT)
-#else
-/* BSS setup */
-#endif
-
-/* MMC/SD IP block */
-#define CONFIG_ROCKCHIP_SDHCI_MAX_FREQ 200000000
-
-/* RAW SD card / eMMC locations. */
-
/* FAT sd card locations. */
#define CFG_SYS_SDRAM_BASE 0
#define SDRAM_MAX_SIZE 0xf8000000
"x_bootcmd_usb=usb start\0" \
"x_bootargs_root=root=/dev/mtdblock3 rw rootfstype=jffs2\0"
-/*
- * Ethernet Driver configuration
- */
-#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
-#define CONFIG_PHY_BASE_ADR 0
-
#endif /* _CONFIG_SHEEVAPLUG_H */
#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024)
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
-/* FLASH */
-#define CONFIG_SPI_FLASH_QUAD
-
/* SH Ether */
#define CONFIG_SH_ETHER_USE_PORT 0
#define CONFIG_SH_ETHER_PHY_ADDR 0x1
#include <configs/exynos5-dt-common.h>
#include <configs/exynos5-common.h>
-#define CONFIG_SMDK5420 /* which is in a SMDK5420 */
-
#define CFG_SYS_SDRAM_BASE 0x20000000
/* DRAM Memory Banks */
/* FLASH and environment organization */
-#define RESERVE_BLOCK_SIZE (512)
-#define BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
-
/* Ethernet Controllor Driver */
#ifdef CONFIG_CMD_NET
#define CONFIG_ENV_SROM_BANK 1
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SR1500 */
/* Ethernet on SoC (EMAC) */
-#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII
/* The PHY is autodetected, so no MII PHY address is needed here */
#define PHY_ANEG_TIMEOUT 8000
-/* Enable SPI NOR flash reset, needed for SPI booting */
-#define CONFIG_SPI_N25Q256A_RESET
-
-/* Environment setting for SPI flash */
-
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>
#ifndef __CONFIG_H
#define __CONFIG_H
-/* High Level Configuration Options */
-#define CONFIG_SOCRATES 1
-
/*
* Only possible on E500 Version 2 or newer cores.
*/
#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
-#define CONFIG_VERY_BIG_RAM
/* I2C addresses of SPD EEPROMs */
#define SPD_EEPROM_ADDRESS 0x50 /* CTLR 0 DIMM 0 */
/* SCIF */
#define CONFIG_SCIF_A
-/* SPI */
-#define CONFIG_SPI_FLASH_QUAD
-
/* SH Ether */
#define CONFIG_SH_ETHER_USE_PORT 0
#define CONFIG_SH_ETHER_PHY_ADDR 0x1
#define CFG_SYS_SDRAM_BASE (0x80000000) /* Start address of DDR3 */
#define PHYS_SDRAM_SIZE (0x7c000000) /* Default size (2GB - Secure memory) */
-#define CONFIG_VERY_BIG_RAM /* SynQuacer supports up to 64GB */
#define CONFIG_MAX_MEM_MAPPED PHYS_SDRAM_SIZE
#define SQ_DRAMINFO_BASE (0x2e00ffc0) /* DRAM info from TF-A */
#define CONFIG_TEGRA_ENABLE_UARTD
#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
-/* Environment in eMMC, at the end of 2nd "boot sector" */
-
-/* SPI */
-#define CONFIG_TEGRA_SLINK_CTRLS 6
-#define CONFIG_SPI_FLASH_SIZE (4 << 20)
-
#include "tegra-common-post.h"
#endif /* __CONFIG_H */
/* Environment in eMMC, at the end of 2nd "boot sector" */
-/* SPI */
-#define CONFIG_SPI_FLASH_SIZE (4 << 20)
-
#include "tegra-common-post.h"
#endif /* __CONFIG_H */
/* USB device */
-/* Ethernet Hardware */
-#define CONFIG_MACB_SEARCH_PHY
-
#ifdef CONFIG_SPI_BOOT
/* bootstrap + u-boot + env + linux in serial flash */
/* Use our own mapping for the VInCo platform */
#ifndef __CONFIG_X86_COMMON_H
#define __CONFIG_X86_COMMON_H
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-/* Generic TPM interfaced through LPC bus */
-#define CONFIG_TPM_TIS_BASE_ADDRESS 0xfed40000
-
-/*-----------------------------------------------------------------------
- * Serial Configuration
- */
-
-/*
- * Miscellaneous configurable options
- */
-
/*-----------------------------------------------------------------------
* CPU Features
*/
#define CONFIG_FEC_ENET_DEV 0
#define CONFIG_FEC_MXC_PHYADDR 0x0
-#define CONFIG_UBOOT_SECTOR_START 0x2
-#define CONFIG_UBOOT_SECTOR_COUNT 0x3fe
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
"image=zImage\0" \
"bootz; " \
"fi;\0" \
"uboot=ccv/u-boot.imx\0" \
- "uboot_start="__stringify(CONFIG_UBOOT_SECTOR_START)"\0" \
- "uboot_size="__stringify(CONFIG_UBOOT_SECTOR_COUNT)"\0" \
+ "uboot_start=0x2\0" \
+ "uboot_size=0x3fe\0" \
"update_uboot=if tftp ${uboot}; then " \
"if itest ${filesize} > 0; then " \
"mmc dev 0 1;" \
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