arm: mvebu: Enable NAND controller on MVEBU SoC's

This patch enables the NAND controller on the Armada XP/38x and provides
a new function that returns the NAND controller input clock. This
function will be used by the MVEBU NAND driver.

As part of this patch, the multiple BIT macro definitions are moved
to a common place in soc.h.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Peter Morrow <peter@senient.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>

diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index fa82067ba8f8b29b0efea0d8ce8fdf7424a24b75..38e15aa7b67b07a9b6e97e9b20deffa88a557c7c 100644 (file)
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c
@@ -241,6 +241,16 @@ int arch_cpu_init(void)
         */
        mvebu_mbus_probe(windows, ARRAY_SIZE(windows));
 
+       if (mvebu_soc_family() == MVEBU_SOC_AXP) {
+               /* Enable GBE0, GBE1, LCD and NFC PUP */
+               clrsetbits_le32(ARMADA_XP_PUP_ENABLE, 0,
+                               GE0_PUP_EN | GE1_PUP_EN | LCD_PUP_EN |
+                               NAND_PUP_EN | SPI_PUP_EN);
+       }
+
+       /* Enable NAND and NAND arbiter */
+       clrsetbits_le32(MVEBU_SOC_DEV_MUX_REG, 0, NAND_EN | NAND_ARBITER_EN);
+
        /* Disable MBUS error propagation */
        clrsetbits_le32(SOC_COHERENCY_FABRIC_CTRL_REG, MBUS_ERR_PROP_EN, 0);
 
@@ -248,6 +258,13 @@ int arch_cpu_init(void)
 }
 #endif /* CONFIG_ARCH_CPU_INIT */
 
+u32 mvebu_get_nand_clock(void)
+{
+       return CONFIG_SYS_MVEBU_PLL_CLOCK /
+               ((readl(MVEBU_CORE_DIV_CLK_CTRL(1)) &
+                 NAND_ECC_DIVCKL_RATIO_MASK) >> NAND_ECC_DIVCKL_RATIO_OFFS);
+}
+
 /*
  * SOC specific misc init
  */

diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h
index 674fdaa0d34ceb8520fbf485a86fa581cf774903..6fa41736e2aa140c354bd61bc9d3fc6a03e33bd7 100644 (file)
--- a/arch/arm/mach-mvebu/include/mach/cpu.h
+++ b/arch/arm/mach-mvebu/include/mach/cpu.h
@@ -117,6 +117,7 @@ unsigned int mvebu_sdram_bs(enum memory_bank bank);
 void mvebu_sdram_size_adjust(enum memory_bank bank);
 int mvebu_mbus_probe(struct mbus_win windows[], int count);
 int mvebu_soc_family(void);
+u32 mvebu_get_nand_clock(void);
 
 int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks);
 

diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h
index a29e5dcedca751cda21d01fe15a361ce257dfec3..6115d6e58dcd4128c5217bd879149c985d18acf8 100644 (file)
--- a/arch/arm/mach-mvebu/include/mach/soc.h
+++ b/arch/arm/mach-mvebu/include/mach/soc.h
@@ -11,6 +11,8 @@
 #ifndef _MVEBU_SOC_H
 #define _MVEBU_SOC_H
 
+#define BIT(x)                 (1 << (x))
+
 #define SOC_MV78460_ID         0x7846
 #define SOC_88F6810_ID         0x6810
 #define SOC_88F6820_ID         0x6820
@@ -25,6 +27,9 @@
 #define CONFIG_SYS_TCLK                250000000       /* 250MHz */
 #endif
 
+/* Armada XP PLL frequency (used for NAND clock generation) */
+#define CONFIG_SYS_MVEBU_PLL_CLOCK     2000000000
+
 /* SOC specific definations */
 #define INTREG_BASE            0xd0000000
 #define INTREG_BASE_ADDR_REG   (INTREG_BASE + 0x20080)
@@ -53,6 +58,7 @@
 #define MVEBU_GPIO1_BASE       (MVEBU_REGISTER(0x18140))
 #define MVEBU_GPIO2_BASE       (MVEBU_REGISTER(0x18180))
 #define MVEBU_SYSTEM_REG_BASE  (MVEBU_REGISTER(0x18200))
+#define MVEBU_CLOCK_BASE       (MVEBU_REGISTER(0x18700))
 #define MVEBU_CPU_WIN_BASE     (MVEBU_REGISTER(0x20000))
 #define MVEBU_SDRAM_BASE       (MVEBU_REGISTER(0x20180))
 #define MVEBU_TIMER_BASE       (MVEBU_REGISTER(0x20300))
@@ -64,6 +70,7 @@
 #define MVEBU_EGIGA1_BASE      (MVEBU_REGISTER(0x74000))
 #define MVEBU_AXP_SATA_BASE    (MVEBU_REGISTER(0xa0000))
 #define MVEBU_SATA0_BASE       (MVEBU_REGISTER(0xa8000))
+#define MVEBU_NAND_BASE                (MVEBU_REGISTER(0xd0000))
 #define MVEBU_SDIO_BASE                (MVEBU_REGISTER(0xd8000))
 
 #define SOC_COHERENCY_FABRIC_CTRL_REG  (MVEBU_REGISTER(0x20200))
@@ -72,6 +79,21 @@
 #define MBUS_BRIDGE_WIN_CTRL_REG (MVEBU_REGISTER(0x20250))
 #define MBUS_BRIDGE_WIN_BASE_REG (MVEBU_REGISTER(0x20254))
 
+#define MVEBU_SOC_DEV_MUX_REG  (MVEBU_SYSTEM_REG_BASE + 0x08)
+#define NAND_EN                        BIT(0)
+#define NAND_ARBITER_EN                BIT(27)
+
+#define ARMADA_XP_PUP_ENABLE   (MVEBU_SYSTEM_REG_BASE + 0x44c)
+#define GE0_PUP_EN             BIT(0)
+#define GE1_PUP_EN             BIT(1)
+#define LCD_PUP_EN             BIT(2)
+#define NAND_PUP_EN            BIT(4)
+#define SPI_PUP_EN             BIT(5)
+
+#define MVEBU_CORE_DIV_CLK_CTRL(i)     (MVEBU_CLOCK_BASE + ((i) * 0x8))
+#define NAND_ECC_DIVCKL_RATIO_OFFS     8
+#define NAND_ECC_DIVCKL_RATIO_MASK     (0x3F << NAND_ECC_DIVCKL_RATIO_OFFS)
+
 #define SDRAM_MAX_CS           4
 #define SDRAM_ADDR_MASK                0xFF000000
 

diff --git a/arch/arm/mach-mvebu/mbus.c b/arch/arm/mach-mvebu/mbus.c
index 71fa69325724a392b838c90aeb04faea81982e1c..771cce6fa3b7a381d8400bc196f018fee897439f 100644 (file)
--- a/arch/arm/mach-mvebu/mbus.c
+++ b/arch/arm/mach-mvebu/mbus.c
@@ -55,8 +55,6 @@
 #include <linux/compat.h>
 #include <linux/mbus.h>
 
-#define BIT(nr)                        (1UL << (nr))
-
 /* DDR target is the same on all platforms */
 #define TARGET_DDR             0
 

diff --git a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c
index e661fa129671d3ef1cdd9d4dd65abfb604d3f566..0eb17f62a2c1c7f024000f74fbe5124f7127a8d6 100644 (file)
--- a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c
+++ b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c
@@ -15,8 +15,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define BIT(nr)                                (1UL << (nr))
-
 #define ETH_PHY_CTRL_REG               0
 #define ETH_PHY_CTRL_POWER_DOWN_BIT    11
 #define ETH_PHY_CTRL_POWER_DOWN_MASK   (1 << ETH_PHY_CTRL_POWER_DOWN_BIT)

diff --git a/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c b/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c
index 00ca878873d92a807a92a5af7778119eb80609c5..78c7b7e4e6bdf76f13a10205edb1fe5fcd2c51e2 100644 (file)
--- a/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c
+++ b/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c
@@ -12,8 +12,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define BIT(nr)                                (1UL << (nr))
-
 #define ETH_PHY_CTRL_REG               0
 #define ETH_PHY_CTRL_POWER_DOWN_BIT    11
 #define ETH_PHY_CTRL_POWER_DOWN_MASK   (1 << ETH_PHY_CTRL_POWER_DOWN_BIT)

diff --git a/drivers/net/mvneta.c b/drivers/net/mvneta.c
index efaae167feffc904c08fe76cb8a8ffdf296ebd35..38ad14eff96dc8a62dc0bba4af2b5a41d8986583 100644 (file)
--- a/drivers/net/mvneta.c
+++ b/drivers/net/mvneta.c
@@ -41,7 +41,6 @@
        printf(fmt, ##args)
 
 #define CONFIG_NR_CPUS         1
-#define BIT(nr)                        (1UL << (nr))
 #define ETH_HLEN               14      /* Total octets in header */
 
 /* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */