pinctrl: sunxi: move PIO_BASE into sunxi_gpio.h

On the Allwinner platform we were describing a quite comprehensive
memory map in a per-SoC header unser arch/arm.
In the old days that was used by every driver, but nowadays it should
only be needed by SPL drivers (not using the DT). Many addresses in
there were never used, and some are not needed anymore.

To avoid a dependency on CPU specific headers in an arch specific
directory, move the definition of the pinctroller MMIO base address into
the sunxi_gpio.h header, because the SPL routines for GPIO should be the
only one needing this address.
This is a first step towards getting rid of cpu_sun[x]i.h completely,
and allows to remove the inclusion of that file from the sunxi_gpio.h
header.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>

diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
index f7ecc790dbf0976969ac0f237c366dfbe31f6fa5..d6fe51f24bcbcd3007d68dfde875e47580c94cdc 100644 (file)
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
@@ -91,7 +91,6 @@
 
 #define SUNXI_CCM_BASE                 0x01c20000
 #define SUNXI_INTC_BASE                        0x01c20400
-#define SUNXI_PIO_BASE                 0x01c20800
 #define SUNXI_TIMER_BASE               0x01c20c00
 #ifndef CONFIG_SUNXI_GEN_SUN6I
 #define SUNXI_PWM_BASE                 0x01c20e00
@@ -210,7 +209,6 @@ defined(CONFIG_MACH_SUN50I)
 
 #define SUNXI_R_TWI_BASE               0x01f02400
 #define SUNXI_R_UART_BASE              0x01f02800
-#define SUNXI_R_PIO_BASE               0x01f02c00
 #define SUN6I_P2WI_BASE                        0x01f03400
 #define SUNXI_RSB_BASE                 0x01f03400
 

diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h
index d9cf8ae042883990a6e07c502c59b105f7fa2c09..9b6bf8436016a5c275c21e4f27d9fa95e3f8f7a4 100644 (file)
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h
@@ -22,7 +22,6 @@
 #define SUNXI_SIDC_BASE                        0x03006000
 #define SUNXI_SID_BASE                 0x03006200
 #define SUNXI_TIMER_BASE               0x03009000
-#define SUNXI_PIO_BASE                 0x0300B000
 #define SUNXI_PSI_BASE                 0x0300C000
 
 #define SUNXI_GIC400_BASE              0x03020000
@@ -68,7 +67,6 @@
 #define SUNXI_R_CPUCFG_BASE            0x07000400
 #define SUNXI_PRCM_BASE                        0x07010000
 #define SUNXI_R_WDOG_BASE              0x07020400
-#define SUNXI_R_PIO_BASE               0x07022000
 #define SUNXI_R_UART_BASE              0x07080000
 #define SUNXI_R_TWI_BASE               0x07081400
 

diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
index 9c2d11b5901cbec64be90f838cb7a43345a04535..20025be231987be7efa3f4a1636432183b410559 100644 (file)
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
@@ -81,7 +81,6 @@
 /* APB0 Module */
 #define SUNXI_CCM_BASE                 (REGS_APB0_BASE + 0x0000)
 #define SUNXI_CCMMODULE_BASE           (REGS_APB0_BASE + 0x0400)
-#define SUNXI_PIO_BASE                 (REGS_APB0_BASE + 0x0800)
 #define SUNXI_TIMER_BASE               (REGS_APB0_BASE + 0x0C00)
 #define SUNXI_PWM_BASE                 (REGS_APB0_BASE + 0x1400)
 #define SUNXI_LRADC_BASE               (REGS_APB0_BASE + 0x1800)
@@ -102,7 +101,6 @@
 /* RCPUS Module */
 #define SUNXI_PRCM_BASE                        (REGS_RCPUS_BASE + 0x1400)
 #define SUNXI_R_UART_BASE              (REGS_RCPUS_BASE + 0x2800)
-#define SUNXI_R_PIO_BASE               (REGS_RCPUS_BASE + 0x2c00)
 #define SUNXI_RSB_BASE                 (REGS_RCPUS_BASE + 0x3400)
 
 /* Misc. */

diff --git a/include/sunxi_gpio.h b/include/sunxi_gpio.h
index e0fb5b5da63f0b11bd381661ea4c9754e2ee3a33..c1fdf7ea1d7f6eb008ba03d2d9b1e72ef0e5d49c 100644 (file)
--- a/include/sunxi_gpio.h
+++ b/include/sunxi_gpio.h
@@ -12,7 +12,17 @@
 #define _SUNXI_GPIO_H
 
 #include <linux/types.h>
-#include <asm/arch/cpu.h>
+
+#if defined(CONFIG_MACH_SUN9I)
+#define SUNXI_PIO_BASE         0x06000800
+#define SUNXI_R_PIO_BASE       0x08002c00
+#elif defined(CONFIG_SUN50I_GEN_H6)
+#define SUNXI_PIO_BASE         0x0300b000
+#define SUNXI_R_PIO_BASE       0x07022000
+#else
+#define SUNXI_PIO_BASE         0x01c20800
+#define SUNXI_R_PIO_BASE       0x01f02c00
+#endif
 
 /*
  * sunxi has 9 banks of gpio, they are: