arm: dts: stm32mp15: alignment with v5.18

Device tree alignment with Linux kernel v5.18-rc2:
- ARM: dts: stm32: Add support for the emtrion emSBC-Argon
  (only the pincontrol part)
- ARM: dts: stm32: Drop duplicate status okay from DHCOM gpioc node
- ARM: dts: stm32: add st,stm32-sdmmc2 compatible on stm32mp151
- ARM: dts: stm32: fix AV96 board SAI2 pin muxing on stm32mp15
- ARM: dts: stm32: use exti 19 as main interrupt to support RTC wakeup on
  stm32mp157
- ARM: dts: stm32: add DMA configuration to UART nodes on stm32mp151
- ARM: dts: stm32: keep uart4 behavior on *
- ARM: dts: stm32: Correct masks for GIC PPI interrupts on stm32mp15

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>

diff --git a/arch/arm/dts/stm32mp15-pinctrl.dtsi b/arch/arm/dts/stm32mp15-pinctrl.dtsi
index 6161f5906ec11b3debd2edb8108ad3fa20fc66ba..f0d66d8c6e3b3bff92fcc377c5acf3b919d040b6 100644 (file)
--- a/arch/arm/dts/stm32mp15-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp15-pinctrl.dtsi
@@ -338,6 +338,47 @@
                };
        };
 
+       ethernet0_rmii_pins_b: rmii-1 {
+               pins1 {
+                       pinmux = <STM32_PINMUX('B', 5, AF0)>, /* ETH1_CLK */
+                               <STM32_PINMUX('C', 1, AF11)>, /* ETH1_MDC */
+                               <STM32_PINMUX('G', 13, AF11)>, /* ETH1_TXD0 */
+                               <STM32_PINMUX('G', 14, AF11)>; /* ETH1_TXD1 */
+                       bias-disable;
+                       drive-push-pull;
+                       slew-rate = <1>;
+               };
+               pins2 {
+                       pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH1_MDIO */
+                       bias-disable;
+                       drive-push-pull;
+                       slew-rate = <0>;
+               };
+               pins3 {
+                       pinmux = <STM32_PINMUX('A', 7, AF11)>, /* ETH1_CRS_DV */
+                               <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RXD0 */
+                               <STM32_PINMUX('C', 5, AF11)>; /* ETH1_RXD1 */
+                       bias-disable;
+               };
+               pins4 {
+                       pinmux = <STM32_PINMUX('B', 11, AF11)>; /* ETH1_TX_EN */
+               };
+       };
+
+       ethernet0_rmii_sleep_pins_b: rmii-sleep-1 {
+               pins1 {
+                       pinmux = <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */
+                               <STM32_PINMUX('A', 7, ANALOG)>, /* ETH1_CRS_DV */
+                               <STM32_PINMUX('B', 5, ANALOG)>, /* ETH1_CLK */
+                               <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_TX_EN */
+                               <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */
+                               <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RXD0 */
+                               <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RXD1 */
+                               <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_TXD0 */
+                               <STM32_PINMUX('G', 14, ANALOG)>; /* ETH1_TXD1 */
+               };
+       };
+
        fmc_pins_a: fmc-0 {
                pins1 {
                        pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
@@ -927,6 +968,21 @@
                };
        };
 
+       pwm1_pins_b: pwm1-1 {
+               pins {
+                       pinmux = <STM32_PINMUX('E', 9, AF1)>; /* TIM1_CH1 */
+                       bias-pull-down;
+                       drive-push-pull;
+                       slew-rate = <0>;
+               };
+       };
+
+       pwm1_sleep_pins_b: pwm1-sleep-1 {
+               pins {
+                       pinmux = <STM32_PINMUX('E', 9, ANALOG)>; /* TIM1_CH1 */
+               };
+       };
+
        pwm2_pins_a: pwm2-0 {
                pins {
                        pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */
@@ -2042,6 +2098,42 @@
                };
        };
 
+       usart3_pins_d: usart3-3 {
+               pins1 {
+                       pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
+                                <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
+                       bias-disable;
+                       drive-push-pull;
+                       slew-rate = <0>;
+               };
+               pins2 {
+                       pinmux = <STM32_PINMUX('D', 9, AF7)>, /* USART3_RX */
+                                <STM32_PINMUX('D', 11, AF7)>; /* USART3_CTS_NSS */
+                       bias-disable;
+               };
+       };
+
+       usart3_idle_pins_d: usart3-idle-3 {
+               pins1 {
+                       pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
+                                <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
+                                <STM32_PINMUX('D', 11, ANALOG)>; /* USART3_CTS_NSS */
+               };
+               pins2 {
+                       pinmux = <STM32_PINMUX('D', 9, AF7)>; /* USART3_RX */
+                       bias-disable;
+               };
+       };
+
+       usart3_sleep_pins_d: usart3-sleep-3 {
+               pins {
+                       pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
+                                <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
+                                <STM32_PINMUX('D', 11, ANALOG)>, /* USART3_CTS_NSS */
+                                <STM32_PINMUX('D', 9, ANALOG)>; /* USART3_RX */
+               };
+       };
+
        usbotg_hs_pins_a: usbotg-hs-0 {
                pins {
                        pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */

diff --git a/arch/arm/dts/stm32mp15-u-boot.dtsi b/arch/arm/dts/stm32mp15-u-boot.dtsi
index e23d6c7d7ebf145fb165ae4f945c8e0a6df55d77..d9d04743ac81940a58270a684bbfc7eb8a0bf638 100644 (file)
--- a/arch/arm/dts/stm32mp15-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15-u-boot.dtsi
@@ -188,18 +188,6 @@
        #size-cells = <0>;
 };
 
-&sdmmc1 {
-       compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
-};
-
-&sdmmc2 {
-       compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
-};
-
-&sdmmc3 {
-       compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
-};
-
 &usart1 {
        resets = <&rcc USART1_R>;
 };

diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi
index 5a2be0075861e892d05495b7e90d6f4ed7c430aa..e74a5faf4a3c4d20667f37d2d3013f7b0e2ec150 100644 (file)
--- a/arch/arm/dts/stm32mp151.dtsi
+++ b/arch/arm/dts/stm32mp151.dtsi
@@ -63,10 +63,10 @@
 
        timer {
                compatible = "arm,armv7-timer";
-               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-                            <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-                            <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-                            <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
                interrupt-parent = <&intc>;
        };
 
@@ -473,6 +473,9 @@
                        interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&rcc USART2_K>;
                        wakeup-source;
+                       dmas = <&dmamux1 43 0x400 0x15>,
+                              <&dmamux1 44 0x400 0x11>;
+                       dma-names = "rx", "tx";
                        status = "disabled";
                };
 
@@ -482,6 +485,9 @@
                        interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&rcc USART3_K>;
                        wakeup-source;
+                       dmas = <&dmamux1 45 0x400 0x15>,
+                              <&dmamux1 46 0x400 0x11>;
+                       dma-names = "rx", "tx";
                        status = "disabled";
                };
 
@@ -491,6 +497,9 @@
                        interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&rcc UART4_K>;
                        wakeup-source;
+                       dmas = <&dmamux1 63 0x400 0x15>,
+                              <&dmamux1 64 0x400 0x11>;
+                       dma-names = "rx", "tx";
                        status = "disabled";
                };
 
@@ -500,6 +509,9 @@
                        interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&rcc UART5_K>;
                        wakeup-source;
+                       dmas = <&dmamux1 65 0x400 0x15>,
+                              <&dmamux1 66 0x400 0x11>;
+                       dma-names = "rx", "tx";
                        status = "disabled";
                };
 
@@ -606,6 +618,9 @@
                        interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&rcc UART7_K>;
                        wakeup-source;
+                       dmas = <&dmamux1 79 0x400 0x15>,
+                              <&dmamux1 80 0x400 0x11>;
+                       dma-names = "rx", "tx";
                        status = "disabled";
                };
 
@@ -615,6 +630,9 @@
                        interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&rcc UART8_K>;
                        wakeup-source;
+                       dmas = <&dmamux1 81 0x400 0x15>,
+                              <&dmamux1 82 0x400 0x11>;
+                       dma-names = "rx", "tx";
                        status = "disabled";
                };
 
@@ -696,6 +714,9 @@
                        interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&rcc USART6_K>;
                        wakeup-source;
+                       dmas = <&dmamux1 71 0x400 0x15>,
+                              <&dmamux1 72 0x400 0x11>;
+                       dma-names = "rx", "tx";
                        status = "disabled";
                };
 
@@ -1077,7 +1098,7 @@
                };
 
                sdmmc3: mmc@48004000 {
-                       compatible = "arm,pl18x", "arm,primecell";
+                       compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
                        arm,primecell-periphid = <0x00253180>;
                        reg = <0x48004000 0x400>;
                        interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
@@ -1411,7 +1432,7 @@
                };
 
                sdmmc1: mmc@58005000 {
-                       compatible = "arm,pl18x", "arm,primecell";
+                       compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
                        arm,primecell-periphid = <0x00253180>;
                        reg = <0x58005000 0x1000>;
                        interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
@@ -1426,7 +1447,7 @@
                };
 
                sdmmc2: mmc@58007000 {
-                       compatible = "arm,pl18x", "arm,primecell";
+                       compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
                        arm,primecell-periphid = <0x00253180>;
                        reg = <0x58007000 0x1000>;
                        interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
@@ -1590,7 +1611,7 @@
                        reg = <0x5c004000 0x400>;
                        clocks = <&rcc RTCAPB>, <&rcc RTC>;
                        clock-names = "pclk", "rtc_ck";
-                       interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
                        status = "disabled";
                };
 

diff --git a/arch/arm/dts/stm32mp153.dtsi b/arch/arm/dts/stm32mp153.dtsi
index 1c1889b194cfcc719f9ca200a1d1c0660d612388..486084e0b80b5df0fc3c581641918c90c23dbe2a 100644 (file)
--- a/arch/arm/dts/stm32mp153.dtsi
+++ b/arch/arm/dts/stm32mp153.dtsi
@@ -22,6 +22,13 @@
                interrupt-affinity = <&cpu0>, <&cpu1>;
        };
 
+       timer {
+               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+       };
+
        soc {
                m_can1: can@4400e000 {
                        compatible = "bosch,m_can";

diff --git a/arch/arm/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts b/arch/arm/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts
index d3058a036c749f62fcc7f1aae882b637a06ffa0c..1f75f1d451813429e89fc29e264b59b0a69f8a1b 100644 (file)
--- a/arch/arm/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts
+++ b/arch/arm/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts
@@ -43,5 +43,7 @@
        pinctrl-0 = <&uart4_pins_a>;
        pinctrl-1 = <&uart4_sleep_pins_a>;
        pinctrl-2 = <&uart4_idle_pins_a>;
+       /delete-property/dmas;
+       /delete-property/dma-names;
        status = "okay";
 };

diff --git a/arch/arm/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts b/arch/arm/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts
index ec9f1d1cd50fb456615e92913393a49898d155fc..3a1295cfa978880b966ed67dbe99796e01b4f83b 100644 (file)
--- a/arch/arm/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts
+++ b/arch/arm/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts
@@ -43,5 +43,7 @@
        pinctrl-0 = <&uart4_pins_a>;
        pinctrl-1 = <&uart4_sleep_pins_a>;
        pinctrl-2 = <&uart4_idle_pins_a>;
+       /delete-property/dmas;
+       /delete-property/dma-names;
        status = "okay";
 };

diff --git a/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts
index 5670b23812a2165a2ef12a537f300b22e7679473..fae656edd8209a963918fa13cc0b8694897e1aa9 100644 (file)
--- a/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts
+++ b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts
@@ -143,6 +143,8 @@
        pinctrl-0 = <&uart4_pins_a>;
        pinctrl-1 = <&uart4_sleep_pins_a>;
        pinctrl-2 = <&uart4_idle_pins_a>;
+       /delete-property/dmas;
+       /delete-property/dma-names;
        status = "okay";
 };
 
@@ -150,5 +152,7 @@
 &uart8 {
        pinctrl-names = "default";
        pinctrl-0 = <&uart8_pins_a>;
+       /delete-property/dmas;
+       /delete-property/dma-names;
        status = "okay";
 };

diff --git a/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts
index 7a75868164dc065825f1a96cb53e91a9a858b56f..b9d0d3d6ad15bb7e6ed880804e63be798735c394 100644 (file)
--- a/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts
+++ b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts
@@ -44,6 +44,8 @@
        pinctrl-0 = <&uart4_pins_a>;
        pinctrl-1 = <&uart4_sleep_pins_a>;
        pinctrl-2 = <&uart4_idle_pins_a>;
+       /delete-property/dmas;
+       /delete-property/dma-names;
        status = "okay";
 };
 
@@ -51,5 +53,7 @@
 &uart8 {
        pinctrl-names = "default";
        pinctrl-0 = <&uart8_pins_a>;
+       /delete-property/dmas;
+       /delete-property/dma-names;
        status = "okay";
 };

diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts
index f62b46b8dd5e84447da50bc970be073983d05a7a..fe5c8f25cecd80ac16d16891f6223b28425e204d 100644 (file)
--- a/arch/arm/dts/stm32mp157c-ed1.dts
+++ b/arch/arm/dts/stm32mp157c-ed1.dts
@@ -392,6 +392,8 @@
        pinctrl-0 = <&uart4_pins_a>;
        pinctrl-1 = <&uart4_sleep_pins_a>;
        pinctrl-2 = <&uart4_idle_pins_a>;
+       /delete-property/dmas;
+       /delete-property/dma-names;
        status = "okay";
 };
 

diff --git a/arch/arm/dts/stm32mp157c-odyssey.dts b/arch/arm/dts/stm32mp157c-odyssey.dts
index 0e725498dd185f47227766d9782ec92e47d1d8a0..17bcf56f744a0474c5ddde4a614130ada95f1033 100644 (file)
--- a/arch/arm/dts/stm32mp157c-odyssey.dts
+++ b/arch/arm/dts/stm32mp157c-odyssey.dts
@@ -132,6 +132,8 @@
 &uart4 {
        pinctrl-names = "default";
        pinctrl-0 = <&uart4_pins_a>;
+       /delete-property/dmas;
+       /delete-property/dma-names;
        status = "okay";
 };
 

diff --git a/arch/arm/dts/stm32mp15xx-dhcom-drc02.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-drc02.dtsi
index 4b10b013ffd52274fc6ae1cd2dde1c83eddee4f3..35b1034aa3cf63f6cfa438f8f7f7a506e3bd6bf6 100644 (file)
--- a/arch/arm/dts/stm32mp15xx-dhcom-drc02.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcom-drc02.dtsi
@@ -131,6 +131,8 @@
 &usart3 {
        pinctrl-names = "default";
        pinctrl-0 = <&usart3_pins_a>;
+       /delete-property/dmas;
+       /delete-property/dma-names;
        status = "okay";
 };
 
@@ -144,6 +146,8 @@
        pinctrl-names = "default";
        pinctrl-0 = <&uart8_pins_a>;
        rts-gpios = <&gpioe 6 GPIO_ACTIVE_HIGH>;
+       /delete-property/dmas;
+       /delete-property/dma-names;
        status = "okay";
 };
 

diff --git a/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dtsi
index fbf3826933e4dbe5dc1f52a973c4e6018ca25319..5f586f024060fb80f4f5cb7ecdc146b7048241d4 100644 (file)
--- a/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dtsi
@@ -287,6 +287,8 @@
 &usart3 {
        pinctrl-names = "default";
        pinctrl-0 = <&usart3_pins_a>;
+       /delete-property/dmas;
+       /delete-property/dma-names;
        status = "okay";
 };
 
@@ -294,6 +296,8 @@
        pinctrl-names = "default";
        pinctrl-0 = <&uart8_pins_a &uart8_rtscts_pins_a>;
        uart-has-rtscts;
+       /delete-property/dmas;
+       /delete-property/dma-names;
        status = "okay";
 };
 

diff --git a/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dtsi
index ba816ef8b9b25586e13aee1bbeba5d905262e35e..abc595350e71a09905ffc256f6baeee927958438 100644 (file)
--- a/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dtsi
@@ -105,12 +105,16 @@
 &usart3 {
        pinctrl-names = "default";
        pinctrl-0 = <&usart3_pins_a>;
+       /delete-property/dmas;
+       /delete-property/dma-names;
        status = "okay";
 };
 
 &uart8 {
        pinctrl-names = "default";
        pinctrl-0 = <&uart8_pins_a &uart8_rtscts_pins_a>;
+       /delete-property/dmas;
+       /delete-property/dma-names;
        status = "okay";
 };
 

diff --git a/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi
index 8c41f819f77696171d8da706391979983cbaf5b2..83e2c87713f8e06ed5a37e74596f4aa15c2093ad 100644 (file)
--- a/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi
@@ -196,7 +196,6 @@
                          "", "", "DHCOM-E", "",
                          "", "", "", "",
                          "", "", "", "";
-       status = "okay";
 };
 
 &gpiod {
@@ -521,5 +520,7 @@
 &uart4 {
        pinctrl-names = "default";
        pinctrl-0 = <&uart4_pins_a>;
+       /delete-property/dmas;
+       /delete-property/dma-names;
        status = "okay";
 };

diff --git a/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dtsi
index 6885948f3024e753d4785be40338a60c63dd7194..61e17f44ce81549bb83317deee6faad6c0920335 100644 (file)
--- a/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dtsi
@@ -376,6 +376,8 @@
        label = "LS-UART1";
        pinctrl-names = "default";
        pinctrl-0 = <&uart4_pins_b>;
+       /delete-property/dmas;
+       /delete-property/dma-names;
        status = "okay";
 };
 
@@ -385,6 +387,8 @@
        pinctrl-names = "default";
        pinctrl-0 = <&uart7_pins_a>;
        uart-has-rtscts;
+       /delete-property/dmas;
+       /delete-property/dma-names;
        status = "okay";
 };
 
@@ -394,6 +398,8 @@
        pinctrl-0 = <&usart2_pins_a>;
        pinctrl-1 = <&usart2_sleep_pins_a>;
        st,hw-flow-ctrl;
+       /delete-property/dmas;
+       /delete-property/dma-names;
        status = "okay";
 
        bluetooth {

diff --git a/arch/arm/dts/stm32mp15xx-dkx.dtsi b/arch/arm/dts/stm32mp15xx-dkx.dtsi
index f8130bf445171e1a8308c5ee72759ff7121cec11..3d36cac9ed00c43a0e4db48bc3d3a0e6202c55b8 100644 (file)
--- a/arch/arm/dts/stm32mp15xx-dkx.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dkx.dtsi
@@ -658,6 +658,8 @@
        pinctrl-0 = <&uart4_pins_a>;
        pinctrl-1 = <&uart4_sleep_pins_a>;
        pinctrl-2 = <&uart4_idle_pins_a>;
+       /delete-property/dmas;
+       /delete-property/dma-names;
        status = "okay";
 };
 
@@ -666,6 +668,8 @@
        pinctrl-0 = <&uart7_pins_c>;
        pinctrl-1 = <&uart7_sleep_pins_c>;
        pinctrl-2 = <&uart7_idle_pins_c>;
+       /delete-property/dmas;
+       /delete-property/dma-names;
        status = "disabled";
 };