dt-bindings: versal: Add versal reset IDs

The same file is already the part of Linux kernel that's why add it also to
u-boot to be able to use it in source code and DT files.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/1c3bc464536a9bf64a2e8bfe18a938c9cb490620.1657192249.git.michal.simek@amd.com

diff --git a/include/dt-bindings/reset/xlnx-versal-resets.h b/include/dt-bindings/reset/xlnx-versal-resets.h
new file mode 100644 (file)
index 0000000..895424e
--- /dev/null
+++ b/include/dt-bindings/reset/xlnx-versal-resets.h
@@ -0,0 +1,105 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ *  Copyright (C) 2020 Xilinx, Inc.
+ */
+
+#ifndef _DT_BINDINGS_VERSAL_RESETS_H
+#define _DT_BINDINGS_VERSAL_RESETS_H
+
+#define VERSAL_RST_PMC_POR                     (0xc30c001U)
+#define VERSAL_RST_PMC                         (0xc410002U)
+#define VERSAL_RST_PS_POR                      (0xc30c003U)
+#define VERSAL_RST_PL_POR                      (0xc30c004U)
+#define VERSAL_RST_NOC_POR                     (0xc30c005U)
+#define VERSAL_RST_FPD_POR                     (0xc30c006U)
+#define VERSAL_RST_ACPU_0_POR                  (0xc30c007U)
+#define VERSAL_RST_ACPU_1_POR                  (0xc30c008U)
+#define VERSAL_RST_OCM2_POR                    (0xc30c009U)
+#define VERSAL_RST_PS_SRST                     (0xc41000aU)
+#define VERSAL_RST_PL_SRST                     (0xc41000bU)
+#define VERSAL_RST_NOC                         (0xc41000cU)
+#define VERSAL_RST_NPI                         (0xc41000dU)
+#define VERSAL_RST_SYS_RST_1                   (0xc41000eU)
+#define VERSAL_RST_SYS_RST_2                   (0xc41000fU)
+#define VERSAL_RST_SYS_RST_3                   (0xc410010U)
+#define VERSAL_RST_FPD                         (0xc410011U)
+#define VERSAL_RST_PL0                         (0xc410012U)
+#define VERSAL_RST_PL1                         (0xc410013U)
+#define VERSAL_RST_PL2                         (0xc410014U)
+#define VERSAL_RST_PL3                         (0xc410015U)
+#define VERSAL_RST_APU                         (0xc410016U)
+#define VERSAL_RST_ACPU_0                      (0xc410017U)
+#define VERSAL_RST_ACPU_1                      (0xc410018U)
+#define VERSAL_RST_ACPU_L2                     (0xc410019U)
+#define VERSAL_RST_ACPU_GIC                    (0xc41001aU)
+#define VERSAL_RST_RPU_ISLAND                  (0xc41001bU)
+#define VERSAL_RST_RPU_AMBA                    (0xc41001cU)
+#define VERSAL_RST_R5_0                                (0xc41001dU)
+#define VERSAL_RST_R5_1                                (0xc41001eU)
+#define VERSAL_RST_SYSMON_PMC_SEQ_RST          (0xc41001fU)
+#define VERSAL_RST_SYSMON_PMC_CFG_RST          (0xc410020U)
+#define VERSAL_RST_SYSMON_FPD_CFG_RST          (0xc410021U)
+#define VERSAL_RST_SYSMON_FPD_SEQ_RST          (0xc410022U)
+#define VERSAL_RST_SYSMON_LPD                  (0xc410023U)
+#define VERSAL_RST_PDMA_RST1                   (0xc410024U)
+#define VERSAL_RST_PDMA_RST0                   (0xc410025U)
+#define VERSAL_RST_ADMA                                (0xc410026U)
+#define VERSAL_RST_TIMESTAMP                   (0xc410027U)
+#define VERSAL_RST_OCM                         (0xc410028U)
+#define VERSAL_RST_OCM2_RST                    (0xc410029U)
+#define VERSAL_RST_IPI                         (0xc41002aU)
+#define VERSAL_RST_SBI                         (0xc41002bU)
+#define VERSAL_RST_LPD                         (0xc41002cU)
+#define VERSAL_RST_QSPI                                (0xc10402dU)
+#define VERSAL_RST_OSPI                                (0xc10402eU)
+#define VERSAL_RST_SDIO_0                      (0xc10402fU)
+#define VERSAL_RST_SDIO_1                      (0xc104030U)
+#define VERSAL_RST_I2C_PMC                     (0xc104031U)
+#define VERSAL_RST_GPIO_PMC                    (0xc104032U)
+#define VERSAL_RST_GEM_0                       (0xc104033U)
+#define VERSAL_RST_GEM_1                       (0xc104034U)
+#define VERSAL_RST_SPARE                       (0xc104035U)
+#define VERSAL_RST_USB_0                       (0xc104036U)
+#define VERSAL_RST_UART_0                      (0xc104037U)
+#define VERSAL_RST_UART_1                      (0xc104038U)
+#define VERSAL_RST_SPI_0                       (0xc104039U)
+#define VERSAL_RST_SPI_1                       (0xc10403aU)
+#define VERSAL_RST_CAN_FD_0                    (0xc10403bU)
+#define VERSAL_RST_CAN_FD_1                    (0xc10403cU)
+#define VERSAL_RST_I2C_0                       (0xc10403dU)
+#define VERSAL_RST_I2C_1                       (0xc10403eU)
+#define VERSAL_RST_GPIO_LPD                    (0xc10403fU)
+#define VERSAL_RST_TTC_0                       (0xc104040U)
+#define VERSAL_RST_TTC_1                       (0xc104041U)
+#define VERSAL_RST_TTC_2                       (0xc104042U)
+#define VERSAL_RST_TTC_3                       (0xc104043U)
+#define VERSAL_RST_SWDT_FPD                    (0xc104044U)
+#define VERSAL_RST_SWDT_LPD                    (0xc104045U)
+#define VERSAL_RST_USB                         (0xc104046U)
+#define VERSAL_RST_DPC                         (0xc208047U)
+#define VERSAL_RST_PMCDBG                      (0xc208048U)
+#define VERSAL_RST_DBG_TRACE                   (0xc208049U)
+#define VERSAL_RST_DBG_FPD                     (0xc20804aU)
+#define VERSAL_RST_DBG_TSTMP                   (0xc20804bU)
+#define VERSAL_RST_RPU0_DBG                    (0xc20804cU)
+#define VERSAL_RST_RPU1_DBG                    (0xc20804dU)
+#define VERSAL_RST_HSDP                                (0xc20804eU)
+#define VERSAL_RST_DBG_LPD                     (0xc20804fU)
+#define VERSAL_RST_CPM_POR                     (0xc30c050U)
+#define VERSAL_RST_CPM                         (0xc410051U)
+#define VERSAL_RST_CPMDBG                      (0xc208052U)
+#define VERSAL_RST_PCIE_CFG                    (0xc410053U)
+#define VERSAL_RST_PCIE_CORE0                  (0xc410054U)
+#define VERSAL_RST_PCIE_CORE1                  (0xc410055U)
+#define VERSAL_RST_PCIE_DMA                    (0xc410056U)
+#define VERSAL_RST_CMN                         (0xc410057U)
+#define VERSAL_RST_L2_0                                (0xc410058U)
+#define VERSAL_RST_L2_1                                (0xc410059U)
+#define VERSAL_RST_ADDR_REMAP                  (0xc41005aU)
+#define VERSAL_RST_CPI0                                (0xc41005bU)
+#define VERSAL_RST_CPI1                                (0xc41005cU)
+#define VERSAL_RST_XRAM                                (0xc30c05dU)
+#define VERSAL_RST_AIE_ARRAY                   (0xc10405eU)
+#define VERSAL_RST_AIE_SHIM                    (0xc10405fU)
+
+#endif