mv_ddr: ddr3: fix tRAS timimg parameter

Based on the JEDEC standard JESD79-3F. The tRAS timings should include
the highest speed bins at a given frequency. This is similar to commit
683c67b ("mv_ddr: ddr3: fix tfaw timimg parameter") where the wrong
comparison was used in the initial implementation.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
[https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/15]
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/drivers/ddr/marvell/a38x/ddr3_training_db.c b/drivers/ddr/marvell/a38x/ddr3_training_db.c
index 111a8586c6e35464bef7282f6db13ede3d1bdbbb..b2f11a839961525c4a26b57a63e94f5719cf3d28 100644 (file)
--- a/drivers/ddr/marvell/a38x/ddr3_training_db.c
+++ b/drivers/ddr/marvell/a38x/ddr3_training_db.c
@@ -420,13 +420,13 @@ unsigned int mv_ddr_speed_bin_timing_get(enum mv_ddr_speed_bin index, enum mv_dd
                result = speed_bin_table_t_rcd_t_rp[index];
                break;
        case SPEED_BIN_TRAS:
-               if (index < SPEED_BIN_DDR_1066G)
+               if (index <= SPEED_BIN_DDR_1066G)
                        result = 37500;
-               else if (index < SPEED_BIN_DDR_1333J)
+               else if (index <= SPEED_BIN_DDR_1333J)
                        result = 36000;
-               else if (index < SPEED_BIN_DDR_1600K)
+               else if (index <= SPEED_BIN_DDR_1600K)
                        result = 35000;
-               else if (index < SPEED_BIN_DDR_1866M)
+               else if (index <= SPEED_BIN_DDR_1866M)
                        result = 34000;
                else
                        result = 33000;