git.dujemihanovic.xyz Git - u-boot.git/commit

]> git.dujemihanovic.xyz Git - u-boot.git/commit

author	Pragnesh Patel <pragnesh.patel@sifive.com>
	Fri, 29 May 2020 06:03:32 +0000 (11:33 +0530)
committer	Andes <uboot@andestech.com>
	Thu, 4 Jun 2020 01:44:09 +0000 (09:44 +0800)
commit	329e023868f28fd2cda31dc788017ef7c48fb1a8
tree	82ee7dbb4ca86483275286099b026e7b7bf71d73	tree \| snapshot
parent	1ba43d29eb626ee813650baf12a72a31ed2bffca	commit \| diff

riscv: sifive: dts: fu540: set ethernet clock rate

Set ethernet clock rate to 125 Mhz so that it will work with 1000Mbps,
Earlier this is done by FSBL. With this change We can remove the
ethernet clock rate code from FSBL.

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>

arch/riscv/dts/fu540-c000-u-boot.dtsi

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