From d8169c9f3ba04f5e470008c59afa3161ce683524 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk <wd@pollux.denx.de> Date: Sun, 12 Mar 2006 18:06:37 +0100 Subject: [PATCH] Fix bad register definitions for LTX971 PHY on MPC85xx boards. Patch by Gerhard Jaeger, 21 Jun 2005 --- CHANGELOG | 3 +++ drivers/tsec.h | 12 ++++++------ 2 files changed, 9 insertions(+), 6 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index 704bb0548e..272463280b 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,9 @@ Changes since U-Boot 1.1.4: ====================================================================== +* Fix bad register definitions for LTX971 PHY on MPC85xx boards. + Patch by Gerhard Jaeger, 21 Jun 2005 + * Add netconsole and some more commands to RPXlite_DW board Patch by Sam Song, 19 Jun 2005 diff --git a/drivers/tsec.h b/drivers/tsec.h index c26fcc0e73..e3bbff03bf 100644 --- a/drivers/tsec.h +++ b/drivers/tsec.h @@ -161,12 +161,12 @@ #define MIIM_DM9161_10BTCSR_INIT 0x7800 /* LXT971 Status 2 registers */ -#define MIIM_LXT971_SR2 17 /* Status Register 2 */ -#define MIIM_LXT971_SR2_SPEED_MASK 0xf000 -#define MIIM_LXT971_SR2_10HDX 0x1000 /* 10 Mbit half duplex selected */ -#define MIIM_LXT971_SR2_10FDX 0x2000 /* 10 Mbit full duplex selected */ -#define MIIM_LXT971_SR2_100HDX 0x4000 /* 100 Mbit half duplex selected */ -#define MIIM_LXT971_SR2_100FDX 0x8000 /* 100 Mbit full duplex selected */ +#define MIIM_LXT971_SR2 0x11 /* Status Register 2 */ +#define MIIM_LXT971_SR2_SPEED_MASK 0x4200 +#define MIIM_LXT971_SR2_10HDX 0x0000 /* 10 Mbit half duplex selected */ +#define MIIM_LXT971_SR2_10FDX 0x0200 /* 10 Mbit full duplex selected */ +#define MIIM_LXT971_SR2_100HDX 0x4000 /* 100 Mbit half duplex selected */ +#define MIIM_LXT971_SR2_100FDX 0x4200 /* 100 Mbit full duplex selected */ #define MIIM_READ_COMMAND 0x00000001 -- 2.39.5