From d1e5b4065ee14a6dbabd9318a8f73194c6536d6e Mon Sep 17 00:00:00 2001
From: Thierry Reding <treding@nvidia.com>
Date: Tue, 9 Dec 2014 22:25:23 -0700
Subject: [PATCH] ARM: tegra: Enable non-cached memory

Some boards, most notably those with a PCIe ethernet NIC, require this
to avoid cache coherency problems. Since the option adds very little
code and overhead enable it across all Tegra generations. Other drivers
may also start supporting this functionality at some point, so enabling
it now will automatically reap the benefits later on.

Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
---
 include/configs/tegra-common.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h
index 06853285a2..8f1e370915 100644
--- a/include/configs/tegra-common.h
+++ b/include/configs/tegra-common.h
@@ -47,7 +47,9 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN		(4 << 20)	/* 4MB  */
-#define CONFIG_SYS_MALLOC_F_LEN	(1 << 10)
+#define CONFIG_SYS_MALLOC_F_LEN		(1 << 10)
+
+#define CONFIG_SYS_NONCACHED_MEMORY	(1 << 20)       /* 1 MiB */
 
 /*
  * NS16550 Configuration
-- 
2.39.5