From c24e8e2bb34da1fa17d19acf2b542dba5dfb7e47 Mon Sep 17 00:00:00 2001 From: Tom Rini <trini@konsulko.com> Date: Wed, 15 Jun 2022 12:03:55 -0400 Subject: [PATCH] Convert CONFIG_SYS_DDR_RAW_TIMING to Kconfig This converts the following to Kconfig: CONFIG_SYS_DDR_RAW_TIMING Signed-off-by: Tom Rini <trini@konsulko.com> --- README | 6 ------ configs/P1010RDB-PA_36BIT_NAND_defconfig | 1 + configs/P1010RDB-PA_36BIT_NOR_defconfig | 1 + configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 1 + configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 1 + configs/P1010RDB-PA_NAND_defconfig | 1 + configs/P1010RDB-PA_NOR_defconfig | 1 + configs/P1010RDB-PA_SDCARD_defconfig | 1 + configs/P1010RDB-PA_SPIFLASH_defconfig | 1 + configs/P1010RDB-PB_36BIT_NAND_defconfig | 1 + configs/P1010RDB-PB_36BIT_NOR_defconfig | 1 + configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 1 + configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 1 + configs/P1010RDB-PB_NAND_defconfig | 1 + configs/P1010RDB-PB_NOR_defconfig | 1 + configs/P1010RDB-PB_SDCARD_defconfig | 1 + configs/P1010RDB-PB_SPIFLASH_defconfig | 1 + configs/P1020RDB-PC_36BIT_NAND_defconfig | 1 + configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 1 + configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 1 + configs/P1020RDB-PC_36BIT_defconfig | 1 + configs/P1020RDB-PC_NAND_defconfig | 1 + configs/P1020RDB-PC_SDCARD_defconfig | 1 + configs/P1020RDB-PC_SPIFLASH_defconfig | 1 + configs/P1020RDB-PC_defconfig | 1 + configs/P1020RDB-PD_NAND_defconfig | 1 + configs/P1020RDB-PD_SDCARD_defconfig | 1 + configs/P1020RDB-PD_SPIFLASH_defconfig | 1 + configs/P1020RDB-PD_defconfig | 1 + configs/P2020RDB-PC_36BIT_NAND_defconfig | 1 + configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 1 + configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 1 + configs/P2020RDB-PC_36BIT_defconfig | 1 + configs/P2020RDB-PC_NAND_defconfig | 1 + configs/P2020RDB-PC_SDCARD_defconfig | 1 + configs/P2020RDB-PC_SPIFLASH_defconfig | 1 + configs/P2020RDB-PC_defconfig | 1 + configs/ls1021aqds_nand_defconfig | 1 + configs/ls1021aqds_nor_SECURE_BOOT_defconfig | 1 + configs/ls1021aqds_nor_defconfig | 1 + configs/ls1021aqds_nor_lpuart_defconfig | 1 + configs/ls1021aqds_qspi_defconfig | 1 + configs/ls1021aqds_sdcard_ifc_defconfig | 1 + configs/ls1021aqds_sdcard_qspi_defconfig | 1 + configs/ls1043ardb_SECURE_BOOT_defconfig | 1 + configs/ls1043ardb_defconfig | 1 + configs/ls1043ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1043ardb_tfa_defconfig | 1 + drivers/ddr/fsl/Kconfig | 7 +++++++ include/configs/P1010RDB.h | 1 - include/configs/T102xRDB.h | 1 - include/configs/ls1021aqds.h | 4 ---- include/configs/ls1043ardb.h | 1 - include/configs/ls2080a_common.h | 4 ---- include/configs/p1_p2_rdb_pc.h | 1 - 55 files changed, 54 insertions(+), 18 deletions(-) diff --git a/README b/README index c3308ec4d9..f3d4a9c2b2 100644 --- a/README +++ b/README @@ -2079,12 +2079,6 @@ Low Level (hardware related) configuration options: one, specify here. Note that the value must resolve to something your driver can deal with. -- CONFIG_SYS_DDR_RAW_TIMING - Get DDR timing information from other than SPD. Common with - soldered DDR chips onboard without SPD. DDR raw timing - parameters are extracted from datasheet and hard-coded into - header files or board specific files. - - CONFIG_FSL_DDR_INTERACTIVE Enable interactive DDR debugging. See doc/README.fsl-ddr. diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig index a57da3e22a..121bb0cec9 100644 --- a/configs/P1010RDB-PA_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig @@ -82,6 +82,7 @@ CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_TPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig index 14f322f58f..ee6952e170 100644 --- a/configs/P1010RDB-PA_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig @@ -49,6 +49,7 @@ CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_COMMON_INIT_DDR=y CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig index ba9c8a0509..8343e94748 100644 --- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig @@ -71,6 +71,7 @@ CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig index 5948f699bc..7336c3096e 100644 --- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig @@ -74,6 +74,7 @@ CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig index ef7cc29b13..e77a790f52 100644 --- a/configs/P1010RDB-PA_NAND_defconfig +++ b/configs/P1010RDB-PA_NAND_defconfig @@ -81,6 +81,7 @@ CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_TPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig index 2fe5b61d2c..08cde4e210 100644 --- a/configs/P1010RDB-PA_NOR_defconfig +++ b/configs/P1010RDB-PA_NOR_defconfig @@ -48,6 +48,7 @@ CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_COMMON_INIT_DDR=y CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig index 573f799f5d..06e39bc74c 100644 --- a/configs/P1010RDB-PA_SDCARD_defconfig +++ b/configs/P1010RDB-PA_SDCARD_defconfig @@ -70,6 +70,7 @@ CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig index 086c34d016..b241d1f719 100644 --- a/configs/P1010RDB-PA_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_SPIFLASH_defconfig @@ -73,6 +73,7 @@ CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig index 850a9746d8..7b67bc087f 100644 --- a/configs/P1010RDB-PB_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig @@ -83,6 +83,7 @@ CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_TPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig index 9ae73502c4..59125f2448 100644 --- a/configs/P1010RDB-PB_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig @@ -50,6 +50,7 @@ CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_COMMON_INIT_DDR=y CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig index e26ffa2ae4..c37eba1771 100644 --- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig @@ -72,6 +72,7 @@ CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig index 1f3adaa5b2..906b48f243 100644 --- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig @@ -75,6 +75,7 @@ CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig index b5d0017372..726de84104 100644 --- a/configs/P1010RDB-PB_NAND_defconfig +++ b/configs/P1010RDB-PB_NAND_defconfig @@ -82,6 +82,7 @@ CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_TPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig index 5118e83b6e..3d4fb2cc7c 100644 --- a/configs/P1010RDB-PB_NOR_defconfig +++ b/configs/P1010RDB-PB_NOR_defconfig @@ -49,6 +49,7 @@ CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_COMMON_INIT_DDR=y CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig index 1c8ebac496..ca5abd4ed1 100644 --- a/configs/P1010RDB-PB_SDCARD_defconfig +++ b/configs/P1010RDB-PB_SDCARD_defconfig @@ -71,6 +71,7 @@ CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig index 8354163bde..e8d963bdb2 100644 --- a/configs/P1010RDB-PB_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_SPIFLASH_defconfig @@ -74,6 +74,7 @@ CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig index 4def5dc496..c2a9a15cfa 100644 --- a/configs/P1020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig @@ -80,6 +80,7 @@ CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xFF800C21 CONFIG_SYS_OR0_PRELIM=0xFFFF8396 diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig index 87f4bf2c50..d4ef3d9812 100644 --- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig @@ -70,6 +70,7 @@ CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig index f5332eabc8..216429e989 100644 --- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig @@ -73,6 +73,7 @@ CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig index d6af6a8298..7593507894 100644 --- a/configs/P1020RDB-PC_36BIT_defconfig +++ b/configs/P1020RDB-PC_36BIT_defconfig @@ -49,6 +49,7 @@ CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig index 2301d62d17..2789ce9901 100644 --- a/configs/P1020RDB-PC_NAND_defconfig +++ b/configs/P1020RDB-PC_NAND_defconfig @@ -79,6 +79,7 @@ CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xFF800C21 CONFIG_SYS_OR0_PRELIM=0xFFFF8396 diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig index 87fb78c182..944bf2379c 100644 --- a/configs/P1020RDB-PC_SDCARD_defconfig +++ b/configs/P1020RDB-PC_SDCARD_defconfig @@ -69,6 +69,7 @@ CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig index 65de103a52..8ed7a7ad36 100644 --- a/configs/P1020RDB-PC_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_SPIFLASH_defconfig @@ -72,6 +72,7 @@ CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig index 4c3751e66e..49c6037d4b 100644 --- a/configs/P1020RDB-PC_defconfig +++ b/configs/P1020RDB-PC_defconfig @@ -48,6 +48,7 @@ CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig index 9164276f94..f428c68e68 100644 --- a/configs/P1020RDB-PD_NAND_defconfig +++ b/configs/P1020RDB-PD_NAND_defconfig @@ -82,6 +82,7 @@ CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=2 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xFF800C21 CONFIG_SYS_OR0_PRELIM=0xFFFF8796 diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig index 74d1235375..9eab122f7a 100644 --- a/configs/P1020RDB-PD_SDCARD_defconfig +++ b/configs/P1020RDB-PD_SDCARD_defconfig @@ -72,6 +72,7 @@ CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=2 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEC001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig index 11c9e11aae..ea2784da17 100644 --- a/configs/P1020RDB-PD_SPIFLASH_defconfig +++ b/configs/P1020RDB-PD_SPIFLASH_defconfig @@ -75,6 +75,7 @@ CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=2 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEC001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig index d38c3e00e2..b63da1e9e2 100644 --- a/configs/P1020RDB-PD_defconfig +++ b/configs/P1020RDB-PD_defconfig @@ -51,6 +51,7 @@ CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=2 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEC001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig index 459da473f6..4dacb20a7c 100644 --- a/configs/P2020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig @@ -84,6 +84,7 @@ CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xFF800C21 CONFIG_SYS_OR0_PRELIM=0xFFFF8396 diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig index 3bc28d9d34..2c4c548373 100644 --- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig @@ -74,6 +74,7 @@ CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig index 6158455af3..ee6768b901 100644 --- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig @@ -77,6 +77,7 @@ CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig index 8b52134162..2b5bc85160 100644 --- a/configs/P2020RDB-PC_36BIT_defconfig +++ b/configs/P2020RDB-PC_36BIT_defconfig @@ -53,6 +53,7 @@ CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig index 117382fe88..022684cc40 100644 --- a/configs/P2020RDB-PC_NAND_defconfig +++ b/configs/P2020RDB-PC_NAND_defconfig @@ -83,6 +83,7 @@ CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xFF800C21 CONFIG_SYS_OR0_PRELIM=0xFFFF8396 diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig index 9c101e9737..ca0c9025c7 100644 --- a/configs/P2020RDB-PC_SDCARD_defconfig +++ b/configs/P2020RDB-PC_SDCARD_defconfig @@ -73,6 +73,7 @@ CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig index 4216eecf26..2bc755b83d 100644 --- a/configs/P2020RDB-PC_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_SPIFLASH_defconfig @@ -76,6 +76,7 @@ CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig index e15213a9cb..fef773cb16 100644 --- a/configs/P2020RDB-PC_defconfig +++ b/configs/P2020RDB-PC_defconfig @@ -52,6 +52,7 @@ CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig index cfa81baff6..9ab66cd53c 100644 --- a/configs/ls1021aqds_nand_defconfig +++ b/configs/ls1021aqds_nand_defconfig @@ -95,6 +95,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_SYS_FSL_DDR3=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig index ad7e390b5c..d72af5de15 100644 --- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig @@ -62,6 +62,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_SYS_FSL_DDR3=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig index 1434817e1c..42708b70f6 100644 --- a/configs/ls1021aqds_nor_defconfig +++ b/configs/ls1021aqds_nor_defconfig @@ -65,6 +65,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_SYS_FSL_DDR3=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig index 9bfbe2eff9..925b376086 100644 --- a/configs/ls1021aqds_nor_lpuart_defconfig +++ b/configs/ls1021aqds_nor_lpuart_defconfig @@ -65,6 +65,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_SYS_FSL_DDR3=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig index 02d056f4e6..4e24e43c2f 100644 --- a/configs/ls1021aqds_qspi_defconfig +++ b/configs/ls1021aqds_qspi_defconfig @@ -62,6 +62,7 @@ CONFIG_FSL_CAAM=y CONFIG_SYS_FSL_DDR3=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig index 164e8b0176..d5f6c5c25c 100644 --- a/configs/ls1021aqds_sdcard_ifc_defconfig +++ b/configs/ls1021aqds_sdcard_ifc_defconfig @@ -93,6 +93,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_SYS_FSL_DDR3=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig index 8a6357b0b2..addd100b2b 100644 --- a/configs/ls1021aqds_sdcard_qspi_defconfig +++ b/configs/ls1021aqds_sdcard_qspi_defconfig @@ -89,6 +89,7 @@ CONFIG_FSL_CAAM=y CONFIG_SYS_FSL_DDR3=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig index 7f4729fe7d..aeebd383af 100644 --- a/configs/ls1043ardb_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_SECURE_BOOT_defconfig @@ -45,6 +45,7 @@ CONFIG_ETHPRIME="FM1@DTSEC3" CONFIG_DM=y # CONFIG_DDR_SPD is not set CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig index 454f3dccbb..243a03030a 100644 --- a/configs/ls1043ardb_defconfig +++ b/configs/ls1043ardb_defconfig @@ -49,6 +49,7 @@ CONFIG_DM=y CONFIG_FSL_CAAM=y # CONFIG_DDR_SPD is not set CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig index 34f6952f43..e92c09976d 100644 --- a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig @@ -44,6 +44,7 @@ CONFIG_ETHPRIME="FM1@DTSEC3" CONFIG_DM=y # CONFIG_DDR_SPD is not set CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/ls1043ardb_tfa_defconfig b/configs/ls1043ardb_tfa_defconfig index 5d36183195..e065c72366 100644 --- a/configs/ls1043ardb_tfa_defconfig +++ b/configs/ls1043ardb_tfa_defconfig @@ -51,6 +51,7 @@ CONFIG_DM=y CONFIG_FSL_CAAM=y # CONFIG_DDR_SPD is not set CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig index 6a29b23bab..d93ed8d2fe 100644 --- a/drivers/ddr/fsl/Kconfig +++ b/drivers/ddr/fsl/Kconfig @@ -175,6 +175,13 @@ config ECC_INIT_VIA_DDRCONTROLLER Use the DDR controller to auto initialize memory. If not enabled, the DMA controller is responsible for doing this. +config SYS_DDR_RAW_TIMING + bool "Get DDR timing information from something other than SPD" + help + This is common with soldered DDR chips onboard without SPD. DDR raw + timing parameters are extracted from datasheet and hard-coded into + header files or board specific files. + endif menu "PowerPC / M68K initial memory controller definitions (FLASH, SDRAM, etc)" diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 94fa3174de..200b88050c 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -109,7 +109,6 @@ #define CONFIG_L2_CACHE /* toggle L2 cache */ /* DDR Setup */ -#define CONFIG_SYS_DDR_RAW_TIMING #define SPD_EEPROM_ADDRESS 0x52 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 9d68f2568d..2ccfd87bfb 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -129,7 +129,6 @@ #define SPD_EEPROM_ADDRESS 0x51 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ #elif defined(CONFIG_TARGET_T1023RDB) -#define CONFIG_SYS_DDR_RAW_TIMING #define CONFIG_SYS_SDRAM_SIZE 2048 #endif diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index dd389a9e16..012b47116b 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -24,10 +24,6 @@ #define SPD_EEPROM_ADDRESS 0x51 -#ifndef CONFIG_SYS_FSL_DDR4 -#define CONFIG_SYS_DDR_RAW_TIMING -#endif - #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index f39a940655..411721c125 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -13,7 +13,6 @@ /* Physical Memory Map */ #ifndef CONFIG_SPL -#define CONFIG_SYS_DDR_RAW_TIMING #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index f9eb829cda..d2978713e6 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -16,10 +16,6 @@ /* Link Definitions */ -#ifndef CONFIG_SYS_FSL_DDR4 -#define CONFIG_SYS_DDR_RAW_TIMING -#endif - #define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */ #define CONFIG_VERY_BIG_RAM diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 6bc8a6aca0..cb1b170a45 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -115,7 +115,6 @@ #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ -#define CONFIG_SYS_DDR_RAW_TIMING #define SPD_EEPROM_ADDRESS 0x52 #if defined(CONFIG_TARGET_P1020RDB_PD) -- 2.39.5