--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2024 Arm Limited
+ */
+
+.global save_boot_params
+save_boot_params:
+ /* The firmware provided FDT address via x1 */
+ adr x8, fw_dtb_pointer
+ str x1, [x8]
+
+ b save_boot_params_ret
#include <config.h>
#include <dm.h>
#include <dm/platform_data/serial_pl01x.h>
+#include <env.h>
#include <asm/armv8/mmu.h>
#include <asm/global_data.h>
-
-static const struct pl01x_serial_plat serial_plat = {
- .base = UART0_BASE,
- .type = TYPE_PL011,
- .clock = CFG_PL011_CLOCK,
-};
-
-U_BOOT_DRVINFO(total_compute_serials) = {
- .name = "serial_pl01x",
- .plat = &serial_plat,
-};
+#include <asm/system.h>
static struct mm_region total_compute_mem_map[] = {
{
struct mm_region *mem_map = total_compute_mem_map;
+/*
+ * Push the variable into the .data section so that it
+ * does not get cleared later.
+ */
+unsigned long __section(".data") fw_dtb_pointer;
+
+void *board_fdt_blob_setup(int *err)
+{
+ *err = 0;
+ if (fdt_magic(fw_dtb_pointer) != FDT_MAGIC) {
+ *err = -ENXIO;
+ return NULL;
+ }
+
+ return (void *)fw_dtb_pointer;
+}
+
int board_init(void)
{
return 0;
int dram_init(void)
{
- gd->ram_size = PHYS_SDRAM_1_SIZE;
- return 0;
+ return fdtdec_setup_mem_size_base();
}
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
-
- return 0;
+ return fdtdec_setup_memory_banksize();
}
/* Nothing to be done here as handled by PSCI interface */
/* Link Definitions */
-/* AP non-secure UART base address */
-#define UART0_BASE 0x2A400000
-
-/* PL011 Serial Configuration */
-#define CFG_PL011_CLOCK 7372800
-
-/* Miscellaneous configurable options */
-
-/* Physical Memory Map */
-#define PHYS_SDRAM_1 0x80000000
-/* Top 48MB reserved for secure world use */
-#define DRAM_SEC_SIZE 0x03000000
-#define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE
-#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
-
-#define PHYS_SDRAM_2 0x8080000000
-#define PHYS_SDRAM_2_SIZE 0x180000000
-
#define CFG_EXTRA_ENV_SETTINGS \
"bootm_size=0x20000000\0" \
"load_addr=0xa0000000\0" \