From be24fc780727bf008844d255fc25f2d23afa7812 Mon Sep 17 00:00:00 2001 From: Stefan Agner <stefan.agner@toradex.com> Date: Mon, 25 Mar 2019 17:25:10 +0100 Subject: [PATCH] colibri_vf: adjust timing according to data sheet Using the DDR Validation tool in Processor Expert uncovered two timing inconsistencies. Since those timings are related to the suspend mode they do not affect or change regular memory behaviour. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com> --- board/toradex/colibri_vf/colibri_vf.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c index 9c5bf4951b..3e39912f91 100644 --- a/board/toradex/colibri_vf/colibri_vf.c +++ b/board/toradex/colibri_vf/colibri_vf.c @@ -101,15 +101,21 @@ int dram_init(void) .tras_lockout = 0, .tdal = 12, .bstlen = 3, - .tdll = 512, + .tdll = 512, /* not applicable since freq. scaling + * is not used + */ .trp_ab = 6, .tref = 3120, .trfc = 64, .tref_int = 0, .tpdex = 3, .txpdll = 10, - .txsnr = 48, - .txsr = 468, + .txsnr = 68, /* changed to conform to JEDEC + * specifications + */ + .txsr = 506, /* changed to conform to JEDEC + * specifications + */ .cksrx = 5, .cksre = 5, .freq_chg_en = 0, -- 2.39.5