From b58ab56d14f242850142a49e2a62a80389b3a11e Mon Sep 17 00:00:00 2001 From: Marek Vasut <marex@denx.de> Date: Thu, 6 Jul 2023 23:32:27 +0200 Subject: [PATCH] ARM: stm32: Inhibit PDDS because CSTBYDIS is set The PWR_MPUCR CSTBYDIS bit is set, therefore the CA cores can never enter CStandby state and would always end up in CStop state. Clear the PDDS bit, which indicates the CA cores can enter CStandby state as it makes little sense to keep it set with CSTBYDIS also set. This does however fix a problem too. When both PWR_MPUCR and PWR_MCUCR PDDS bits are set, then the chip enters CStandby state even though the PWR_MCUCR CSTBYDIS is set. Clearing the PWR_MPUCR PDDS prevents that from happening. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> --- arch/arm/mach-stm32mp/psci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-stm32mp/psci.c b/arch/arm/mach-stm32mp/psci.c index 39b5200949..8cdeb0ab3f 100644 --- a/arch/arm/mach-stm32mp/psci.c +++ b/arch/arm/mach-stm32mp/psci.c @@ -729,7 +729,7 @@ void __secure psci_system_suspend(u32 __always_unused function_id, setbits_le32(STM32_RCC_BASE + RCC_MP_CIER, RCC_MP_CIFR_WKUPF); setbits_le32(STM32_PWR_BASE + PWR_MPUCR, - PWR_MPUCR_CSSF | PWR_MPUCR_CSTDBYDIS | PWR_MPUCR_PDDS); + PWR_MPUCR_CSSF | PWR_MPUCR_CSTDBYDIS); saved_mcudivr = readl(STM32_RCC_BASE + RCC_MCUDIVR); saved_pll3cr = readl(STM32_RCC_BASE + RCC_PLL3CR); -- 2.39.5