From aceac0c52bd25e1e96de5b3a31873eebdc1f5ed8 Mon Sep 17 00:00:00 2001 From: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Date: Thu, 11 Jul 2024 13:59:39 +0530 Subject: [PATCH] clk: zynqmp: Add set_rate support for display clocks If "assigned-clock-rates" property is included in the device tree, display driver probe is getting failed, as dp_video_ref till dp_stc_ref clocks are missing from set rate function, adding them to fix the probe failure. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Link: https://lore.kernel.org/r/20240711082939.29260-1-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com> --- drivers/clk/clk_zynqmp.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c index 97f3b999d7..a8239e228c 100644 --- a/drivers/clk/clk_zynqmp.c +++ b/drivers/clk/clk_zynqmp.c @@ -726,6 +726,7 @@ static ulong zynqmp_clk_set_rate(struct clk *clk, ulong rate) case gem_tsu: case qspi_ref ... can1_ref: case usb0_bus_ref ... usb3_dual_ref: + case dp_video_ref ... dp_stc_ref: return zynqmp_clk_set_peripheral_rate(priv, id, rate, two_divs); default: -- 2.39.5