From 734af242c20b10b6fc690836123c5d0389b7e2a0 Mon Sep 17 00:00:00 2001 From: Stefano Babic <sbabic@denx.de> Date: Tue, 17 Jun 2014 16:47:40 +0200 Subject: [PATCH] OMAP: disable gpmc timeout safely for reenabling gpmc timeout is disabled and the reset counter is set to 0. However, if later a driver activates the timeout setting the reset to a valid value, the old reset value with zero is still valid for the first access. In fact, the timeout block loads the reset counter after a successful access. Found on a am335x board with a FPGA connected to the GPMC bus together with the NAND. When the FPGA driver in kernel activates the timeout, the system hangs at the first access by the NAND driver. Signed-off-by: Stefano Babic <sbabic@denx.de> --- arch/arm/cpu/armv7/omap-common/mem-common.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/omap-common/mem-common.c b/arch/arm/cpu/armv7/omap-common/mem-common.c index 11be480abd..5bc7e1f19b 100644 --- a/arch/arm/cpu/armv7/omap-common/mem-common.c +++ b/arch/arm/cpu/armv7/omap-common/mem-common.c @@ -121,7 +121,8 @@ void gpmc_init(void) writel(0x00000008, &gpmc_cfg->sysconfig); writel(0x00000000, &gpmc_cfg->irqstatus); writel(0x00000000, &gpmc_cfg->irqenable); - writel(0x00000000, &gpmc_cfg->timeout_control); + /* disable timeout, set a safe reset value */ + writel(0x00001ff0, &gpmc_cfg->timeout_control); #ifdef CONFIG_NOR writel(0x00000200, &gpmc_cfg->config); #else -- 2.39.5