From 4dbee8a90df613eb517aadbecebd70f168913d30 Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Fri, 5 Oct 2007 07:57:20 +0200
Subject: [PATCH] ppc4xx: 4xx_pcie: Change CFG_PCIE_MEMSIZE to 128MB on Yucca &
Katmai
128MB seems to be the smallest possible value for the memory size
for on PCIe port. With this change now the BAR's of the PCIe cards
are accessible under U-Boot.
One big note: This only works for PCIe port 0 & 1. For port 2 this
currently doesn't work, since the base address is now 0xc0000000
(0xb0000000 + 2 * 0x08000000), and this is already occupied by
CFG_PCIE0_CFGBASE. But solving this issue for port 2 would mean
to change the base addresses completely and this change would have
too much impact right now.
This patch adds debug output to the 4xx pcie driver too.
Signed-off-by: Stefan Roese <sr@denx.de>
---
cpu/ppc4xx/4xx_pcie.c | 25 ++++++++++++++++++++++++-
include/configs/katmai.h | 2 +-
include/configs/yucca.h | 2 +-
3 files changed, 26 insertions(+), 3 deletions(-)
diff --git a/cpu/ppc4xx/4xx_pcie.c b/cpu/ppc4xx/4xx_pcie.c
index 2b3e657806..7ac8ce0d76 100644
--- a/cpu/ppc4xx/4xx_pcie.c
+++ b/cpu/ppc4xx/4xx_pcie.c
@@ -20,6 +20,11 @@
*
*/
+/* define DEBUG for debugging output (obviously ;-)) */
+#if 1
+#define DEBUG
+#endif
+
#include <asm/processor.h>
#include <asm-ppc/io.h>
#include <ppc4xx.h>
@@ -708,7 +713,10 @@ void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port)
* subregions and to enable the outbound translation.
*/
out_le32(mbase + PECFG_POM0LAH, 0x00000000);
- out_le32(mbase + PECFG_POM0LAL, 0x00000000);
+ out_le32(mbase + PECFG_POM0LAL, CFG_PCIE_MEMBASE +
+ port * CFG_PCIE_MEMSIZE);
+ debug("PECFG_POM0LA=%08x.%08x\n", in_le32(mbase + PECFG_POM0LAH),
+ in_le32(mbase + PECFG_POM0LAL));
switch (port) {
case 0:
@@ -718,6 +726,11 @@ void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port)
mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
~(CFG_PCIE_MEMSIZE - 1) | 3);
+ debug("0:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n",
+ mfdcr(DCRN_PEGPL_OMR1BAH(PCIE0)),
+ mfdcr(DCRN_PEGPL_OMR1BAL(PCIE0)),
+ mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE0)),
+ mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE0)));
break;
case 1:
mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), 0x0000000d);
@@ -726,6 +739,11 @@ void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port)
mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
~(CFG_PCIE_MEMSIZE - 1) | 3);
+ debug("1:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n",
+ mfdcr(DCRN_PEGPL_OMR1BAH(PCIE1)),
+ mfdcr(DCRN_PEGPL_OMR1BAL(PCIE1)),
+ mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE1)),
+ mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE1)));
break;
case 2:
mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), 0x0000000d);
@@ -734,6 +752,11 @@ void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port)
mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
~(CFG_PCIE_MEMSIZE - 1) | 3);
+ debug("2:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n",
+ mfdcr(DCRN_PEGPL_OMR1BAH(PCIE2)),
+ mfdcr(DCRN_PEGPL_OMR1BAL(PCIE2)),
+ mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE2)),
+ mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE2)));
break;
}
diff --git a/include/configs/katmai.h b/include/configs/katmai.h
index 7908e5a474..03c3cb3bdf 100644
--- a/include/configs/katmai.h
+++ b/include/configs/katmai.h
@@ -62,7 +62,7 @@
#define CFG_PCI_TARGBASE CFG_PCI_MEMBASE
#define CFG_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */
-#define CFG_PCIE_MEMSIZE 0x01000000
+#define CFG_PCIE_MEMSIZE 0x08000000 /* smallest incr for PCIe port */
#define CFG_PCIE_BASE 0xe0000000 /* PCIe UTL regs */
#define CFG_PCIE0_CFGBASE 0xc0000000
diff --git a/include/configs/yucca.h b/include/configs/yucca.h
index 74033b4aef..6caf21bcb5 100644
--- a/include/configs/yucca.h
+++ b/include/configs/yucca.h
@@ -64,7 +64,7 @@
#define CFG_PCI_TARGBASE CFG_PCI_MEMBASE
#define CFG_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */
-#define CFG_PCIE_MEMSIZE 0x01000000
+#define CFG_PCIE_MEMSIZE 0x08000000 /* smallest incr for PCIe port */
#define CFG_PCIE_BASE 0xe0000000 /* PCIe UTL regs */
#define CFG_PCIE0_CFGBASE 0xc0000000
--
2.39.5