clk: mediatek: mt7988: convert to unified infracfg gates + muxes

Convert to infracfg gates + muxes implementation now that it's
supported.

Drop infracfg-ao nodes and rename all infracfg-ao clocks to infracfg.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>

diff --git a/arch/arm/dts/mt7988.dtsi b/arch/arm/dts/mt7988.dtsi
index 10d5c2a33c3313f159c13f274449677a0d25047d..4695e1db1ad16f35885285b9bb5331f792ad29b4 100644 (file)
--- a/arch/arm/dts/mt7988.dtsi
+++ b/arch/arm/dts/mt7988.dtsi
@@ -97,13 +97,6 @@
                interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
        };
 
-       infracfg_ao_cgs: infracfg_ao_cgs@10001000 {
-               compatible = "mediatek,mt7988-infracfg_ao_cgs", "syscon";
-               reg = <0 0x10001000 0 0x1000>;
-               clock-parent = <&infracfg_ao>;
-               #clock-cells = <1>;
-       };
-
        apmixedsys: apmixedsys@1001e000 {
                compatible = "mediatek,mt7988-fixed-plls", "syscon";
                reg = <0 0x1001e000 0 0x1000>;
@@ -251,7 +244,7 @@
                #clock-cells = <1>;
        };
 
-       infracfg_ao: infracfg@10001000 {
+       infracfg: infracfg@10001000 {
                compatible = "mediatek,mt7988-infracfg", "syscon";
                reg = <0 0x10001000 0 0x1000>;
                clock-parent = <&topckgen>;
@@ -262,9 +255,9 @@
                compatible = "mediatek,hsuart";
                reg = <0 0x11000000 0 0x100>;
                interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART0_CK>;
+               clocks = <&infracfg CK_INFRA_52M_UART0_CK>;
                assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
-                                 <&infracfg_ao CK_INFRA_MUX_UART0_SEL>;
+                                 <&infracfg CK_INFRA_MUX_UART0_SEL>;
                assigned-clock-parents = <&topckgen CK_TOP_XTAL>,
                                         <&topckgen CK_TOP_UART_SEL>;
                status = "disabled";
@@ -274,9 +267,9 @@
                compatible = "mediatek,hsuart";
                reg = <0 0x11000100 0 0x100>;
                interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART1_CK>;
+               clocks = <&infracfg CK_INFRA_52M_UART1_CK>;
                assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
-                                 <&infracfg_ao CK_INFRA_MUX_UART1_SEL>;
+                                 <&infracfg CK_INFRA_MUX_UART1_SEL>;
                assigned-clock-parents = <&topckgen CK_TOP_XTAL>,
                                         <&topckgen CK_TOP_UART_SEL>;
                status = "disabled";
@@ -286,9 +279,9 @@
                compatible = "mediatek,hsuart";
                reg = <0 0x11000200 0 0x100>;
                interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART2_CK>;
+               clocks = <&infracfg CK_INFRA_52M_UART2_CK>;
                assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
-                                 <&infracfg_ao CK_INFRA_MUX_UART2_SEL>;
+                                 <&infracfg CK_INFRA_MUX_UART2_SEL>;
                assigned-clock-parents = <&topckgen CK_TOP_XTAL>,
                                         <&topckgen CK_TOP_UART_SEL>;
                status = "disabled";
@@ -301,8 +294,8 @@
                      <0 0x10217080 0 0x80>;
                interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
                clock-div = <1>;
-               clocks = <&infracfg_ao CK_INFRA_I2C_BCK>,
-                        <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>;
+               clocks = <&infracfg CK_INFRA_I2C_BCK>,
+                        <&infracfg CK_INFRA_66M_AP_DMA_BCK>;
                clock-names = "main", "dma";
                #address-cells = <1>;
                #size-cells = <0>;
@@ -316,8 +309,8 @@
                      <0 0x10217100 0 0x80>;
                interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
                clock-div = <1>;
-               clocks = <&infracfg_ao CK_INFRA_I2C_BCK>,
-                        <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>;
+               clocks = <&infracfg CK_INFRA_I2C_BCK>,
+                        <&infracfg CK_INFRA_66M_AP_DMA_BCK>;
                clock-names = "main", "dma";
                #address-cells = <1>;
                #size-cells = <0>;
@@ -331,8 +324,8 @@
                      <0 0x10217180 0 0x80>;
                interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
                clock-div = <1>;
-               clocks = <&infracfg_ao CK_INFRA_I2C_BCK>,
-                        <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>;
+               clocks = <&infracfg CK_INFRA_I2C_BCK>,
+                        <&infracfg CK_INFRA_66M_AP_DMA_BCK>;
                clock-names = "main", "dma";
                #address-cells = <1>;
                #size-cells = <0>;
@@ -343,16 +336,16 @@
                compatible = "mediatek,mt7988-pwm";
                reg = <0 0x10048000 0 0x1000>;
                #pwm-cells = <2>;
-               clocks = <&infracfg_ao CK_INFRA_66M_PWM_BCK>,
-                        <&infracfg_ao CK_INFRA_66M_PWM_HCK>,
-                        <&infracfg_ao CK_INFRA_66M_PWM_CK1>,
-                        <&infracfg_ao CK_INFRA_66M_PWM_CK2>,
-                        <&infracfg_ao CK_INFRA_66M_PWM_CK3>,
-                        <&infracfg_ao CK_INFRA_66M_PWM_CK4>,
-                        <&infracfg_ao CK_INFRA_66M_PWM_CK5>,
-                        <&infracfg_ao CK_INFRA_66M_PWM_CK6>,
-                        <&infracfg_ao CK_INFRA_66M_PWM_CK7>,
-                        <&infracfg_ao CK_INFRA_66M_PWM_CK8>;
+               clocks = <&infracfg CK_INFRA_66M_PWM_BCK>,
+                        <&infracfg CK_INFRA_66M_PWM_HCK>,
+                        <&infracfg CK_INFRA_66M_PWM_CK1>,
+                        <&infracfg CK_INFRA_66M_PWM_CK2>,
+                        <&infracfg CK_INFRA_66M_PWM_CK3>,
+                        <&infracfg CK_INFRA_66M_PWM_CK4>,
+                        <&infracfg CK_INFRA_66M_PWM_CK5>,
+                        <&infracfg CK_INFRA_66M_PWM_CK6>,
+                        <&infracfg CK_INFRA_66M_PWM_CK7>,
+                        <&infracfg CK_INFRA_66M_PWM_CK8>;
                clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
                              "pwm4","pwm5","pwm6","pwm7","pwm8";
                status = "disabled";
@@ -365,9 +358,9 @@
                      <0 0x11002000 0 0x1000>;
                reg-names = "nfi", "ecc";
                interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&infracfg_ao CK_INFRA_SPINFI>,
-                        <&infracfg_ao CK_INFRA_NFI>,
-                        <&infracfg_ao CK_INFRA_66M_NFI_HCK>;
+               clocks = <&infracfg CK_INFRA_SPINFI>,
+                        <&infracfg CK_INFRA_NFI>,
+                        <&infracfg CK_INFRA_66M_NFI_HCK>;
                clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
                assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>,
                                  <&topckgen CK_TOP_NFI1X_SEL>;
@@ -408,10 +401,10 @@
                             "mediatek,mt7986-mmc";
                reg = <0 0x11230000 0 0x1000>;
                interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&infracfg_ao_cgs CK_INFRA_MSDC400>,
-                        <&infracfg_ao_cgs CK_INFRA_MSDC2_HCK>,
-                        <&infracfg_ao_cgs CK_INFRA_133M_MSDC_0_HCK>,
-                        <&infracfg_ao_cgs CK_INFRA_66M_MSDC_0_HCK>;
+               clocks = <&infracfg CK_INFRA_MSDC400>,
+                        <&infracfg CK_INFRA_MSDC2_HCK>,
+                        <&infracfg CK_INFRA_133M_MSDC_0_HCK>,
+                        <&infracfg CK_INFRA_66M_MSDC_0_HCK>;
                clock-names = "source", "hclk", "source_cg", "axi_cg";
                status = "disabled";
        };

diff --git a/drivers/clk/mediatek/clk-mt7988.c b/drivers/clk/mediatek/clk-mt7988.c
index 7ef03941e244120ffe31233682a09ccf34aaad05..a8d278816bb25b11c49e94bc12f61550f745c91b 100644 (file)
--- a/drivers/clk/mediatek/clk-mt7988.c
+++ b/drivers/clk/mediatek/clk-mt7988.c
@@ -790,6 +790,7 @@ static const struct mtk_clk_tree mt7988_infracfg_clk_tree = {
        .muxes_offs = CK_INFRA_MUX_UART0_SEL,
        .gates_offs = CK_INFRA_PCIE_PERI_26M_CK_P0,
        .muxes = infracfg_mtk_mux,
+       .gates = infracfg_mtk_gates,
        .flags = CLK_BYPASS_XTAL,
        .xtal_rate = 40 * MHZ,
 };
@@ -847,20 +848,9 @@ static const struct udevice_id mt7988_infracfg_compat[] = {
        {}
 };
 
-static const struct udevice_id mt7988_infracfg_ao_cgs_compat[] = {
-       { .compatible = "mediatek,mt7988-infracfg_ao_cgs" },
-       {}
-};
-
 static int mt7988_infracfg_probe(struct udevice *dev)
 {
-       return mtk_common_clk_init(dev, &mt7988_infracfg_clk_tree);
-}
-
-static int mt7988_infracfg_ao_cgs_probe(struct udevice *dev)
-{
-       return mtk_common_clk_gate_init(dev, &mt7988_infracfg_clk_tree,
-                                       infracfg_mtk_gates);
+       return mtk_common_clk_infrasys_init(dev, &mt7988_infracfg_clk_tree);
 }
 
 U_BOOT_DRIVER(mtk_clk_infracfg) = {
@@ -873,16 +863,6 @@ U_BOOT_DRIVER(mtk_clk_infracfg) = {
        .flags = DM_FLAG_PRE_RELOC,
 };
 
-U_BOOT_DRIVER(mtk_clk_infracfg_ao_cgs) = {
-       .name = "mt7988-clock-infracfg_ao_cgs",
-       .id = UCLASS_CLK,
-       .of_match = mt7988_infracfg_ao_cgs_compat,
-       .probe = mt7988_infracfg_ao_cgs_probe,
-       .priv_auto = sizeof(struct mtk_cg_priv),
-       .ops = &mtk_clk_gate_ops,
-       .flags = DM_FLAG_PRE_RELOC,
-};
-
 /* ETHDMA */
 
 static const struct mtk_gate_regs ethdma_cg_regs = {