From 5fe4c0cc6e80cffb6fb91a3c35a8adb6ce4e0e2b Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 14 May 2021 21:34:19 -0400 Subject: [PATCH] ppc: Remove TQM834x board This board has not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove it. Signed-off-by: Tom Rini --- arch/powerpc/cpu/mpc83xx/Kconfig | 6 - board/tqc/tqm834x/Kconfig | 12 - board/tqc/tqm834x/MAINTAINERS | 6 - board/tqc/tqm834x/Makefile | 9 - board/tqc/tqm834x/pci.c | 98 ------- board/tqc/tqm834x/tqm834x.c | 433 ------------------------------- configs/TQM834x_defconfig | 166 ------------ include/configs/TQM834x.h | 277 -------------------- 8 files changed, 1007 deletions(-) delete mode 100644 board/tqc/tqm834x/Kconfig delete mode 100644 board/tqc/tqm834x/MAINTAINERS delete mode 100644 board/tqc/tqm834x/Makefile delete mode 100644 board/tqc/tqm834x/pci.c delete mode 100644 board/tqc/tqm834x/tqm834x.c delete mode 100644 configs/TQM834x_defconfig delete mode 100644 include/configs/TQM834x.h diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index e751daac6e..a67216a2f4 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -89,11 +89,6 @@ config TARGET_KMTEPR2 select VENDOR_KM select KM_ENABLE_FULL_DM_DTS_SUPPORT -config TARGET_TQM834X - bool "Support TQM834x" - select ARCH_MPC8349 - - config TARGET_GAZERBEAM bool "Support gazerbeam" select ARCH_MPC8308 @@ -277,7 +272,6 @@ source "board/freescale/mpc8349emds/Kconfig" source "board/freescale/mpc837xerdb/Kconfig" source "board/ids/ids8313/Kconfig" source "board/keymile/Kconfig" -source "board/tqc/tqm834x/Kconfig" source "board/gdsys/mpc8308/Kconfig" endmenu diff --git a/board/tqc/tqm834x/Kconfig b/board/tqc/tqm834x/Kconfig deleted file mode 100644 index 028b8466e8..0000000000 --- a/board/tqc/tqm834x/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_TQM834X - -config SYS_BOARD - default "tqm834x" - -config SYS_VENDOR - default "tqc" - -config SYS_CONFIG_NAME - default "TQM834x" - -endif diff --git a/board/tqc/tqm834x/MAINTAINERS b/board/tqc/tqm834x/MAINTAINERS deleted file mode 100644 index 543ab1b552..0000000000 --- a/board/tqc/tqm834x/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -TQM834X BOARD -#M: - -S: Maintained -F: board/tqc/tqm834x/ -F: include/configs/TQM834x.h -F: configs/TQM834x_defconfig diff --git a/board/tqc/tqm834x/Makefile b/board/tqc/tqm834x/Makefile deleted file mode 100644 index 3aafbf7928..0000000000 --- a/board/tqc/tqm834x/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# Copyright 2004 Freescale Semiconductor, Inc. - -obj-y += tqm834x.o -obj-$(CONFIG_PCI) += pci.o diff --git a/board/tqc/tqm834x/pci.c b/board/tqc/tqm834x/pci.c deleted file mode 100644 index 92bda60765..0000000000 --- a/board/tqc/tqm834x/pci.c +++ /dev/null @@ -1,98 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static struct pci_region pci1_regions[] = { - { - bus_start: CONFIG_SYS_PCI1_MEM_BASE, - phys_start: CONFIG_SYS_PCI1_MEM_PHYS, - size: CONFIG_SYS_PCI1_MEM_SIZE, - flags: PCI_REGION_MEM | PCI_REGION_PREFETCH - }, - { - bus_start: CONFIG_SYS_PCI1_IO_BASE, - phys_start: CONFIG_SYS_PCI1_IO_PHYS, - size: CONFIG_SYS_PCI1_IO_SIZE, - flags: PCI_REGION_IO - }, - { - bus_start: CONFIG_SYS_PCI1_MMIO_BASE, - phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, - size: CONFIG_SYS_PCI1_MMIO_SIZE, - flags: PCI_REGION_MEM - }, -}; - -/* - * pci_init_board() - * - * NOTICE: MPC8349 internally has two PCI controllers (PCI1 and PCI2) but since - * per TQM834x design physical connections to external devices (PCI sockets) - * are routed only to the PCI1 we do not account for the second one - this code - * supports PCI1 module only. Should support for the PCI2 be required in the - * future it needs a separate pci_controller structure (above) and handling - - * please refer to other boards' implementation for dual PCI host controllers, - * for example board/Marvell/db64360/pci.c, pci_init_board() - * - */ -void -pci_init_board(void) -{ - volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; - volatile law83xx_t *pci_law = immr->sysconf.pcilaw; - struct pci_region *reg[] = { pci1_regions }; - u32 reg32; - - /* - * Configure PCI controller and PCI_CLK_OUTPUT - * - * WARNING! only PCI_CLK_OUTPUT1 is enabled here as this is the one - * line actually used for clocking all external PCI devices in TQM83xx. - * Enabling other PCI_CLK_OUTPUT lines may lead to board's hang for - * unknown reasons - particularly PCI_CLK_OUTPUT6 and PCI_CLK_OUTPUT7 - * are known to hang the board; this issue is under investigation - * (13 oct 05) - */ - reg32 = OCCR_PCICOE1; -#if 0 - /* enabling all PCI_CLK_OUTPUT lines HANGS the board... */ - reg32 = 0xff000000; -#endif - if (clk->spmr & SPMR_CKID) { - /* PCI Clock is half CONFIG_SYS_CLK_FREQ so need to set up OCCR - * fields accordingly */ - reg32 |= (OCCR_PCI1CR | OCCR_PCI2CR); - - reg32 |= (OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 \ - | OCCR_PCICD3 | OCCR_PCICD4 | OCCR_PCICD5 \ - | OCCR_PCICD6 | OCCR_PCICD7); - } - - clk->occr = reg32; - udelay(2000); - - /* Configure PCI Local Access Windows */ - pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; - pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M; - - pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; - pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_16M; - - udelay(2000); - - mpc83xx_pci_init(1, reg); -} diff --git a/board/tqc/tqm834x/tqm834x.c b/board/tqc/tqm834x/tqm834x.c deleted file mode 100644 index 17b4662c16..0000000000 --- a/board/tqc/tqm834x/tqm834x.c +++ /dev/null @@ -1,433 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#define IOSYNC asm("eieio") -#define ISYNC asm("isync") -#define SYNC asm("sync") -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define DDR_MAX_SIZE_PER_CS 0x20000000 - -#if defined(DDR_CASLAT_20) -#define TIMING_CASLAT TIMING_CFG1_CASLAT_20 -#define MODE_CASLAT DDR_MODE_CASLAT_20 -#else -#define TIMING_CASLAT TIMING_CFG1_CASLAT_25 -#define MODE_CASLAT DDR_MODE_CASLAT_25 -#endif - -#define INITIAL_CS_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_12 | \ - CSCONFIG_COL_BIT_9) - -/* External definitions */ -ulong flash_get_size (ulong base, int banknum); - -/* Local functions */ -static int detect_num_flash_banks(void); -static long int get_ddr_bank_size(short cs, long *base); -static void set_cs_bounds(short cs, ulong base, ulong size); -static void set_cs_config(short cs, long config); -static void set_ddr_config(void); - -/* Local variable */ -static volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - -/************************************************************************** - * Board initialzation after relocation to RAM. Used to detect the number - * of Flash banks on TQM834x. - */ -int board_early_init_r (void) { - /* sanity check, IMMARBAR should be mirrored at offset zero of IMMR */ - if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) - return 0; - - /* detect the number of Flash banks */ - return detect_num_flash_banks(); -} - -/************************************************************************** - * DRAM initalization and size detection - */ -int dram_init(void) -{ - long bank_size; - long size; - int cs; - - /* during size detection, set up the max DDRLAW size */ - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE; - im->sysconf.ddrlaw[0].ar = (LAWAR_EN | LAWAR_SIZE_2G); - - /* set CS bounds to maximum size */ - for(cs = 0; cs < 4; ++cs) { - set_cs_bounds(cs, - CONFIG_SYS_SDRAM_BASE + (cs * DDR_MAX_SIZE_PER_CS), - DDR_MAX_SIZE_PER_CS); - - set_cs_config(cs, INITIAL_CS_CONFIG); - } - - /* configure ddr controller */ - set_ddr_config(); - - udelay(200); - - /* enable DDR controller */ - im->ddr.sdram_cfg = (SDRAM_CFG_MEM_EN | - SDRAM_CFG_SREN | - SDRAM_CFG_SDRAM_TYPE_DDR1); - SYNC; - - /* size detection */ - debug("\n"); - size = 0; - for(cs = 0; cs < 4; ++cs) { - debug("\nDetecting Bank%d\n", cs); - - bank_size = get_ddr_bank_size(cs, - (long *)(CONFIG_SYS_SDRAM_BASE + size)); - size += bank_size; - - debug("DDR Bank%d size: %ld MiB\n\n", cs, bank_size >> 20); - - /* exit if less than one bank */ - if(size < DDR_MAX_SIZE_PER_CS) break; - } - - gd->ram_size = size; - - return 0; -} - -/************************************************************************** - * checkboard() - */ -int checkboard (void) -{ - puts("Board: TQM834x\n"); - -#ifdef CONFIG_PCI - volatile immap_t * immr; - u32 w, f; - - immr = (immap_t *)CONFIG_SYS_IMMR; - if (!(immr->reset.rcwh & HRCWH_PCI_HOST)) { - printf("PCI: NOT in host mode..?!\n"); - return 0; - } - - /* get bus width */ - w = 32; - if (immr->reset.rcwh & HRCWH_64_BIT_PCI) - w = 64; - - /* get clock */ - f = gd->pci_clk; - - printf("PCI1: %d bit, %d MHz\n", w, f / 1000000); -#else - printf("PCI: disabled\n"); -#endif - return 0; -} - - -/************************************************************************** - * - * Local functions - * - *************************************************************************/ - -/************************************************************************** - * Detect the number of flash banks (1 or 2). Store it in - * a global variable tqm834x_num_flash_banks. - * Bank detection code based on the Monitor code. - */ -static int detect_num_flash_banks(void) -{ - typedef unsigned long FLASH_PORT_WIDTH; - typedef volatile unsigned long FLASH_PORT_WIDTHV; - FPWV *bank1_base; - FPWV *bank2_base; - FPW bank1_read; - FPW bank2_read; - ulong bank1_size; - ulong bank2_size; - ulong total_size; - - cfi_flash_num_flash_banks = 2; /* assume two banks */ - - /* Get bank 1 and 2 information */ - bank1_size = flash_get_size(CONFIG_SYS_FLASH_BASE, 0); - debug("Bank1 size: %lu\n", bank1_size); - bank2_size = flash_get_size(CONFIG_SYS_FLASH_BASE + bank1_size, 1); - debug("Bank2 size: %lu\n", bank2_size); - total_size = bank1_size + bank2_size; - - if (bank2_size > 0) { - /* Seems like we've got bank 2, but maybe it's mirrored 1 */ - - /* Set the base addresses */ - bank1_base = (FPWV *) (CONFIG_SYS_FLASH_BASE); - bank2_base = (FPWV *) (CONFIG_SYS_FLASH_BASE + bank1_size); - - /* Put bank 2 into CFI command mode and read */ - bank2_base[0x55] = 0x00980098; - IOSYNC; - ISYNC; - bank2_read = bank2_base[0x10]; - - /* Read from bank 1 (it's in read mode) */ - bank1_read = bank1_base[0x10]; - - /* Reset Flash */ - bank1_base[0] = 0x00F000F0; - bank2_base[0] = 0x00F000F0; - - if (bank2_read == bank1_read) { - /* - * Looks like just one bank, but not sure yet. Let's - * read from bank 2 in autosoelect mode. - */ - bank2_base[0x0555] = 0x00AA00AA; - bank2_base[0x02AA] = 0x00550055; - bank2_base[0x0555] = 0x00900090; - IOSYNC; - ISYNC; - bank2_read = bank2_base[0x10]; - - /* Read from bank 1 (it's in read mode) */ - bank1_read = bank1_base[0x10]; - - /* Reset Flash */ - bank1_base[0] = 0x00F000F0; - bank2_base[0] = 0x00F000F0; - - if (bank2_read == bank1_read) { - /* - * In both CFI command and autoselect modes, - * we got the some data reading from Flash. - * There is only one mirrored bank. - */ - cfi_flash_num_flash_banks = 1; - total_size = bank1_size; - } - } - } - - debug("Number of flash banks detected: %d\n", cfi_flash_num_flash_banks); - - /* set OR0 and BR0 */ - set_lbc_or(0, OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_5 | - OR_GPCM_TRLX | (-(total_size) & OR_GPCM_AM)); - set_lbc_br(0, (CONFIG_SYS_FLASH_BASE & BR_BA) | - (BR_MS_GPCM | BR_PS_32 | BR_V)); - - return (0); -} - -/************************************************************************* - * Detect the size of a ddr bank. Sets CS bounds and CS config accordingly. - */ -static long int get_ddr_bank_size(short cs, long *base) -{ - /* This array lists all valid DDR SDRAM configurations, with - * Bank sizes in bytes. (Refer to Table 9-27 in the MPC8349E RM). - * The last entry has to to have size equal 0 and is igonred during - * autodection. Bank sizes must be in increasing order of size - */ - struct { - long row; - long col; - long size; - } conf[] = { - {CSCONFIG_ROW_BIT_12, CSCONFIG_COL_BIT_8, 32 << 20}, - {CSCONFIG_ROW_BIT_12, CSCONFIG_COL_BIT_9, 64 << 20}, - {CSCONFIG_ROW_BIT_12, CSCONFIG_COL_BIT_10, 128 << 20}, - {CSCONFIG_ROW_BIT_13, CSCONFIG_COL_BIT_9, 128 << 20}, - {CSCONFIG_ROW_BIT_13, CSCONFIG_COL_BIT_10, 256 << 20}, - {CSCONFIG_ROW_BIT_13, CSCONFIG_COL_BIT_11, 512 << 20}, - {CSCONFIG_ROW_BIT_14, CSCONFIG_COL_BIT_10, 512 << 20}, - {CSCONFIG_ROW_BIT_14, CSCONFIG_COL_BIT_11, 1024 << 20}, - {0, 0, 0} - }; - - int i; - int detected; - long size; - - detected = -1; - for(i = 0; conf[i].size != 0; ++i) { - - /* set sdram bank configuration */ - set_cs_config(cs, CSCONFIG_EN | conf[i].col | conf[i].row); - - debug("Getting RAM size...\n"); - size = get_ram_size(base, DDR_MAX_SIZE_PER_CS); - - if((size == conf[i].size) && (i == detected + 1)) - detected = i; - - debug("Trying %ld x %ld (%ld MiB) at addr %p, detected: %ld MiB\n", - conf[i].row, - conf[i].col, - conf[i].size >> 20, - base, - size >> 20); - } - - if(detected == -1){ - /* disable empty cs */ - debug("\nNo valid configurations for CS%d, disabling...\n", cs); - set_cs_config(cs, 0); - return 0; - } - - debug("\nDetected configuration %ld x %ld (%ld MiB) at addr %p\n", - conf[detected].row, conf[detected].col, conf[detected].size >> 20, base); - - /* configure cs ro detected params */ - set_cs_config(cs, CSCONFIG_EN | conf[detected].row | - conf[detected].col); - - set_cs_bounds(cs, (long)base, conf[detected].size); - - return(conf[detected].size); -} - -/************************************************************************** - * Sets DDR bank CS bounds. - */ -static void set_cs_bounds(short cs, ulong base, ulong size) -{ - debug("Setting bounds %08lx, %08lx for cs %d\n", base, size, cs); - if(size == 0){ - im->ddr.csbnds[cs].csbnds = 0x00000000; - } else { - im->ddr.csbnds[cs].csbnds = - ((base >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | - (((base + size - 1) >> CSBNDS_EA_SHIFT) & - CSBNDS_EA); - } - SYNC; -} - -/************************************************************************** - * Sets DDR banks CS configuration. - * config == 0x00000000 disables the CS. - */ -static void set_cs_config(short cs, long config) -{ - debug("Setting config %08lx for cs %d\n", config, cs); - im->ddr.cs_config[cs] = config; - SYNC; -} - -/************************************************************************** - * Sets DDR clocks, timings and configuration. - */ -static void set_ddr_config(void) { - /* clock control */ - im->ddr.sdram_clk_cntl = DDR_SDRAM_CLK_CNTL_SS_EN | - DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05; - SYNC; - - /* timing configuration */ - im->ddr.timing_cfg_1 = - (4 << TIMING_CFG1_PRETOACT_SHIFT) | - (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | - (4 << TIMING_CFG1_ACTTORW_SHIFT) | - (5 << TIMING_CFG1_REFREC_SHIFT) | - (3 << TIMING_CFG1_WRREC_SHIFT) | - (3 << TIMING_CFG1_ACTTOACT_SHIFT) | - (1 << TIMING_CFG1_WRTORD_SHIFT) | - (TIMING_CFG1_CASLAT & TIMING_CASLAT); - - im->ddr.timing_cfg_2 = - TIMING_CFG2_CPO_DEF | - (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT); - SYNC; - - /* don't enable DDR controller yet */ - im->ddr.sdram_cfg = - SDRAM_CFG_SREN | - SDRAM_CFG_SDRAM_TYPE_DDR1; - SYNC; - - /* Set SDRAM mode */ - im->ddr.sdram_mode = - ((DDR_MODE_EXT_MODEREG | DDR_MODE_WEAK) << - SDRAM_MODE_ESD_SHIFT) | - ((DDR_MODE_MODEREG | DDR_MODE_BLEN_4) << - SDRAM_MODE_SD_SHIFT) | - ((DDR_MODE_CASLAT << SDRAM_MODE_SD_SHIFT) & - MODE_CASLAT); - SYNC; - - /* Set fast SDRAM refresh rate */ - im->ddr.sdram_interval = - (DDR_REFINT_166MHZ_7US << SDRAM_INTERVAL_REFINT_SHIFT) | - (DDR_BSTOPRE << SDRAM_INTERVAL_BSTOPRE_SHIFT); - SYNC; - - /* Workaround for DDR6 Erratum - * see MPC8349E Device Errata Rev.8, 2/2006 - * This workaround influences the MPC internal "input enables" - * dependent on CAS latency and MPC revision. According to errata - * sheet the internal reserved registers for this workaround are - * not available from revision 2.0 and up. - */ - - /* Get REVID from register SPRIDR. Skip workaround if rev >= 2.0 - * (0x200) - */ - if ((im->sysconf.spridr & SPRIDR_REVID) < 0x200) { - - /* There is a internal reserved register at IMMRBAR+0x2F00 - * which has to be written with a certain value defined by - * errata sheet. - */ - u32 *reserved_p = (u32 *)((u8 *)im + 0x2f00); - -#if defined(DDR_CASLAT_20) - *reserved_p = 0x201c0000; -#else - *reserved_p = 0x202c0000; -#endif - } -} - -#ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *blob, struct bd_info *bd) -{ - ft_cpu_setup(blob, bd); - -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif /* CONFIG_PCI */ - - return 0; -} -#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/configs/TQM834x_defconfig b/configs/TQM834x_defconfig deleted file mode 100644 index c29d8a8be1..0000000000 --- a/configs/TQM834x_defconfig +++ /dev/null @@ -1,166 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x80000000 -CONFIG_ENV_SIZE=0x8000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_SYS_CLK_FREQ=66666000 -CONFIG_MPC83xx=y -CONFIG_HIGH_BATS=y -CONFIG_TARGET_TQM834X=y -CONFIG_SYS_IMMR=0xff400000 -CONFIG_DDR_MC_CLOCK_MODE_1_1=y -CONFIG_SYSTEM_PLL_FACTOR_4_1=y -CONFIG_CORE_PLL_RATIO_2_1=y -CONFIG_PCI_HOST_MODE_ENABLE=y -CONFIG_PCI_INT_ARBITER1_ENABLE=y -CONFIG_BOOT_MEMORY_SPACE_LOW=y -CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y -CONFIG_TSEC1_MODE_GMII=y -CONFIG_TSEC2_MODE_GMII=y -CONFIG_BAT0=y -CONFIG_BAT0_NAME="SDRAM_LOWER" -CONFIG_BAT0_BASE=0x00000000 -CONFIG_BAT0_LENGTH_256_MBYTES=y -CONFIG_BAT0_ACCESS_RW=y -CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y -CONFIG_BAT0_USER_MODE_VALID=y -CONFIG_BAT0_SUPERVISOR_MODE_VALID=y -CONFIG_BAT1=y -CONFIG_BAT1_NAME="SDRAM_UPPER" -CONFIG_BAT1_BASE=0x10000000 -CONFIG_BAT1_LENGTH_256_MBYTES=y -CONFIG_BAT1_ACCESS_RW=y -CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y -CONFIG_BAT1_USER_MODE_VALID=y -CONFIG_BAT1_SUPERVISOR_MODE_VALID=y -CONFIG_BAT2=y -CONFIG_BAT2_NAME="STACK_IN_DCACHE" -CONFIG_BAT2_BASE=0x20000000 -CONFIG_BAT2_ACCESS_RW=y -CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT2_DCACHE_MEMORYCOHERENCE=y -CONFIG_BAT2_USER_MODE_VALID=y -CONFIG_BAT2_SUPERVISOR_MODE_VALID=y -CONFIG_BAT3=y -CONFIG_BAT3_NAME="PCI_MEM_BASE" -CONFIG_BAT3_BASE=0x90000000 -CONFIG_BAT3_LENGTH_256_MBYTES=y -CONFIG_BAT3_ACCESS_RW=y -CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT3_DCACHE_MEMORYCOHERENCE=y -CONFIG_BAT3_USER_MODE_VALID=y -CONFIG_BAT3_SUPERVISOR_MODE_VALID=y -CONFIG_BAT4=y -CONFIG_BAT4_NAME="PCI_MMIO" -CONFIG_BAT4_BASE=0xA0000000 -CONFIG_BAT4_LENGTH_256_MBYTES=y -CONFIG_BAT4_ACCESS_RW=y -CONFIG_BAT4_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT4_ICACHE_GUARDED=y -CONFIG_BAT4_DCACHE_MEMORYCOHERENCE=y -CONFIG_BAT4_DCACHE_GUARDED=y -CONFIG_BAT4_USER_MODE_VALID=y -CONFIG_BAT4_SUPERVISOR_MODE_VALID=y -CONFIG_BAT5=y -CONFIG_BAT5_NAME="PCI_IO" -CONFIG_BAT5_BASE=0xE2000000 -CONFIG_BAT5_LENGTH_16_MBYTES=y -CONFIG_BAT5_ACCESS_RW=y -CONFIG_BAT5_ICACHE_INHIBITED=y -CONFIG_BAT5_ICACHE_GUARDED=y -CONFIG_BAT5_DCACHE_INHIBITED=y -CONFIG_BAT5_DCACHE_GUARDED=y -CONFIG_BAT5_USER_MODE_VALID=y -CONFIG_BAT5_SUPERVISOR_MODE_VALID=y -CONFIG_BAT6=y -CONFIG_BAT6_NAME="IMMR" -CONFIG_BAT6_BASE=0xFF400000 -CONFIG_BAT6_LENGTH_1_MBYTES=y -CONFIG_BAT6_ACCESS_RW=y -CONFIG_BAT6_ICACHE_INHIBITED=y -CONFIG_BAT6_ICACHE_GUARDED=y -CONFIG_BAT6_DCACHE_INHIBITED=y -CONFIG_BAT6_DCACHE_GUARDED=y -CONFIG_BAT6_USER_MODE_VALID=y -CONFIG_BAT6_SUPERVISOR_MODE_VALID=y -CONFIG_BAT7=y -CONFIG_BAT7_NAME="FLASH" -CONFIG_BAT7_BASE=0x80000000 -CONFIG_BAT7_LENGTH_256_MBYTES=y -CONFIG_BAT7_ACCESS_RW=y -CONFIG_BAT7_ICACHE_INHIBITED=y -CONFIG_BAT7_ICACHE_GUARDED=y -CONFIG_BAT7_DCACHE_INHIBITED=y -CONFIG_BAT7_DCACHE_GUARDED=y -CONFIG_BAT7_USER_MODE_VALID=y -CONFIG_BAT7_SUPERVISOR_MODE_VALID=y -CONFIG_LBLAW0=y -CONFIG_LBLAW0_BASE=0x80000000 -CONFIG_LBLAW0_NAME="FLASH" -CONFIG_LBLAW0_LENGTH_1_GBYTES=y -CONFIG_LBLAW1=y -# CONFIG_LBLAW1_ENABLE is not set -CONFIG_LBLAW2=y -# CONFIG_LBLAW2_ENABLE is not set -CONFIG_LBLAW3=y -# CONFIG_LBLAW3_ENABLE is not set -CONFIG_ELBC_BR0_OR0=y -CONFIG_BR0_OR0_NAME="FLASH" -CONFIG_BR0_OR0_BASE=0x80000000 -CONFIG_BR0_PORTSIZE_32BIT=y -CONFIG_OR0_AM_1_GBYTES=y -CONFIG_OR0_SCY_5=y -CONFIG_OR0_CSNT_EARLIER=y -CONFIG_OR0_ACS_QUARTER_CYCLE_EARLIER=y -CONFIG_OR0_TRLX_RELAXED=y -CONFIG_HID0_FINAL_ICE=y -CONFIG_HID2_HBE=y -CONFIG_LCRR_DBYP_PLL_BYPASSED=y -CONFIG_LCRR_CLKDIV_8=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=6 -CONFIG_USE_PREBOOT=y -CONFIG_PREBOOT="echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_EEPROM=y -CONFIG_CMD_I2C=y -CONFIG_CMD_PCI=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_SNTP=y -CONFIG_CMD_DATE=y -CONFIG_CMD_JFFS2=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nor0=TQM834x-0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=TQM834x-0:256k(u-boot),256k(env),1m(kernel),2m(initrd),-(user);" -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_ENV_ADDR=0x80060000 -CONFIG_ENV_ADDR_REDUND=0x80080000 -# CONFIG_MMC is not set -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_EEPRO100=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h deleted file mode 100644 index aa70f01ddd..0000000000 --- a/include/configs/TQM834x.h +++ /dev/null @@ -1,277 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -/* - * TQM8349 board configuration file - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 Family */ - -/* board pre init: do not call, nothing to do */ - -/* detect the number of flash banks */ - -/* - * DDR Setup - */ - /* DDR is system memory*/ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define DDR_CASLAT_25 /* CASLAT set to 2.5 */ -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ -#undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */ - -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ - -/* - * FLASH on the Local Bus - */ -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_BASE 0x80000000 /* start of FLASH */ -#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size in MB */ -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sectors */ - -/* - * FLASH bank number detection - */ - -/* - * When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of - * Flash banks has to be determined at runtime and stored in a gloabl variable - * tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is - * only used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array - * flash_info, and should be made sufficiently large to accomodate the number - * of banks that might actually be detected. Since most (all?) Flash related - * functions use CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on - * the board, it is defined as tqm834x_num_flash_banks. - */ -#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 - -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */ - - -/* disable remaining mappings */ -#define CONFIG_SYS_BR1_PRELIM 0x00000000 -#define CONFIG_SYS_OR1_PRELIM 0x00000000 - -#define CONFIG_SYS_BR2_PRELIM 0x00000000 -#define CONFIG_SYS_OR2_PRELIM 0x00000000 - -#define CONFIG_SYS_BR3_PRELIM 0x00000000 -#define CONFIG_SYS_OR3_PRELIM 0x00000000 - -/* - * Monitor config - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT -#else -# undef CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ - -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - - /* Reserve 384 kB = 3 sect. for Mon */ -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) - /* Reserve 512 kB for malloc */ -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) - -/* - * I2C - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 - -/* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes/write */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */ - -/* I2C RTC */ -#define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ - -/* - * TSEC - */ - -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 -#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) -#define CONFIG_SYS_TSEC2_OFFSET 0x25000 -#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET) - -#if defined(CONFIG_TSEC_ENET) - -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "TSEC1" -#define TSEC1_PHY_ADDR 2 -#define TSEC2_PHY_ADDR 1 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT - -/* Options are: TSEC[0-1] */ -#define CONFIG_ETHPRIME "TSEC0" - -#endif /* CONFIG_TSEC_ENET */ - -#if defined(CONFIG_PCI) - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ - -/* PCI1 host bridge */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x90000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE -#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_MMIO_BASE \ - (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) -#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE -#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_IO_BASE 0xe2000000 -#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE -#define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */ - - -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE - #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_MEM_BASE - #define PCI_IDSEL_NUMBER 0x1c /* slot0 (IDSEL) = 28 */ -#endif - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ - -#endif /* CONFIG_PCI */ - -/* - * Environment - */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ - /* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) - -/* System IO Config */ -#define CONFIG_SYS_SICRH 0 -#define CONFIG_SYS_SICRL SICRL_LDP_A - -/* PCI */ -#ifdef CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE -#endif - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#endif - -/* - * Environment Configuration - */ - - /* default location for tftp and bootm */ -#define CONFIG_LOADADDR 400000 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=tqm834x\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ - "flash_nfs_old=run nfsargs addip addcons;" \ - "bootm ${kernel_addr}\0" \ - "flash_nfs=run nfsargs addip addcons;" \ - "bootm ${kernel_addr} - ${fdt_addr}\0" \ - "flash_self_old=run ramargs addip addcons;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "flash_self=run ramargs addip addcons;" \ - "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ - "net_nfs_old=tftp 400000 ${bootfile};" \ - "run nfsargs addip addcons;bootm\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ - "tftp ${fdt_addr_r} ${fdt_file}; " \ - "run nfsargs addip addcons; " \ - "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "bootfile=tqm834x/uImage\0" \ - "fdtfile=tqm834x/tqm834x.dtb\0" \ - "kernel_addr_r=400000\0" \ - "fdt_addr_r=600000\0" \ - "ramdisk_addr_r=800000\0" \ - "kernel_addr=800C0000\0" \ - "fdt_addr=800A0000\0" \ - "ramdisk_addr=80300000\0" \ - "u-boot=tqm834x/u-boot.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=protect off 80000000 +${filesize};" \ - "era 80000000 +${filesize};" \ - "cp.b 200000 80000000 ${filesize}\0" \ - "upd=run load update\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run flash_self" - -/* - * JFFS2 partitions - */ -/* mtdparts command line support */ - -/* default mtd partition table */ -#endif /* __CONFIG_H */ -- 2.39.5