From: Dylan Hung <dylan_hung@aspeedtech.com>
Date: Tue, 21 Feb 2023 13:01:10 +0000 (+0800)
Subject: clk: ast2600: Keep PLL power on
X-Git-Url: http://git.dujemihanovic.xyz/html/%7B%7B%20%28.OutputFormats.Get?a=commitdiff_plain;h=95f79553849cfb936f8c1e8d453b5a8b73db462c;p=u-boot.git

clk: ast2600: Keep PLL power on

According to the PLL vendor, we should keep the PLL power on, so we
shouldn't toggle the power-down bit during PLL initialization.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
---

diff --git a/drivers/clk/aspeed/clk_ast2600.c b/drivers/clk/aspeed/clk_ast2600.c
index 0df1dc3718..e5ada5b6d4 100644
--- a/drivers/clk/aspeed/clk_ast2600.c
+++ b/drivers/clk/aspeed/clk_ast2600.c
@@ -538,7 +538,7 @@ static uint32_t ast2600_configure_pll(struct ast2600_scu *scu,
 	}
 
 	p_cfg->reg.b.bypass = 0;
-	p_cfg->reg.b.off = 1;
+	p_cfg->reg.b.off = 0;
 	p_cfg->reg.b.reset = 1;
 
 	reg = readl(addr);
@@ -549,7 +549,6 @@ static uint32_t ast2600_configure_pll(struct ast2600_scu *scu,
 	/* write extend parameter */
 	writel(p_cfg->ext_reg, addr_ext);
 	udelay(100);
-	p_cfg->reg.b.off = 0;
 	p_cfg->reg.b.reset = 0;
 	reg &= ~GENMASK(25, 0);
 	reg |= p_cfg->reg.w;