ppc: Remove T4160RDB board

This board has not been converted to CONFIG_DM_PCI by the deadline and is
also missing conversion to CONFIG_DM.  Remove it.  As this is the last
ARCH_T4160 platform, remove that support as well.

Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 876f768e860121cbb78f9f77014a76872769649c..395423582a8e653d7b6f06dcbba6fb7e0ca12427 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -161,13 +161,6 @@ config TARGET_T2080RDB
        imply CMD_SATA
        imply PANIC_HANG
 
-config TARGET_T4160RDB
-       bool "Support T4160RDB"
-       select ARCH_T4160
-       select SUPPORT_SPL
-       select PHYS_64BIT
-       imply PANIC_HANG
-
 config TARGET_T4240RDB
        bool "Support T4240RDB"
        select ARCH_T4240
@@ -732,29 +725,6 @@ config ARCH_T2080
        imply CMD_REGINFO
        imply FSL_SATA
 
-config ARCH_T4160
-       bool
-       select E500MC
-       select E6500
-       select FSL_LAW
-       select SYS_FSL_DDR_VER_47
-       select SYS_FSL_ERRATUM_A004468
-       select SYS_FSL_ERRATUM_A005871
-       select SYS_FSL_ERRATUM_A006379
-       select SYS_FSL_ERRATUM_A006593
-       select SYS_FSL_ERRATUM_A007186
-       select SYS_FSL_ERRATUM_A007798
-       select SYS_FSL_ERRATUM_A009942
-       select SYS_FSL_HAS_DDR3
-       select SYS_FSL_HAS_SEC
-       select SYS_FSL_QORIQ_CHASSIS2
-       select SYS_FSL_SEC_BE
-       select SYS_FSL_SEC_COMPAT_4
-       select SYS_PPC64
-       select FSL_IFC
-       imply CMD_NAND
-       imply CMD_REGINFO
-
 config ARCH_T4240
        bool
        select E500MC
@@ -823,8 +793,7 @@ config NXP_ESBC
 config MAX_CPUS
        int "Maximum number of CPUs permitted for MPC85xx"
        default 12 if ARCH_T4240
-       default 8 if ARCH_P4080 || \
-                    ARCH_T4160
+       default 8 if ARCH_P4080
        default 4 if ARCH_B4860 || \
                     ARCH_P2041 || \
                     ARCH_P3041 || \
@@ -877,7 +846,6 @@ config SYS_CCSRBAR_DEFAULT
                                ARCH_T1040      || \
                                ARCH_T1042      || \
                                ARCH_T2080      || \
-                               ARCH_T4160      || \
                                ARCH_T4240
        default 0xe0000000 if ARCH_QEMU_E500
        help
@@ -1062,7 +1030,6 @@ config SYS_FSL_NUM_LAWS
                        ARCH_P4080      || \
                        ARCH_P5040      || \
                        ARCH_T2080      || \
-                       ARCH_T4160      || \
                        ARCH_T4240
        default 16 if   ARCH_T1024      || \
                        ARCH_T1040      || \
@@ -1142,7 +1109,6 @@ config SYS_FSL_IFC_CLK_DIV
                        ARCH_T1024      || \
                        ARCH_T1040      || \
                        ARCH_T1042      || \
-                       ARCH_T4160      || \
                        ARCH_T4240
        default 1
        help

diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index bbaae0d8454f5dfc53e6d4d60cd5be871bf07f52..993e4873184fc53adb2600cf4ac8996449b941df 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -42,7 +42,6 @@ obj-$(CONFIG_ARCH_P3041) += p3041_ids.o
 obj-$(CONFIG_ARCH_P4080) += p4080_ids.o
 obj-$(CONFIG_ARCH_P5040) += p5040_ids.o
 obj-$(CONFIG_ARCH_T4240) += t4240_ids.o
-obj-$(CONFIG_ARCH_T4160) += t4240_ids.o
 obj-$(CONFIG_ARCH_B4420) += b4860_ids.o
 obj-$(CONFIG_ARCH_B4860) += b4860_ids.o
 obj-$(CONFIG_ARCH_T1040) += t1040_ids.o
@@ -74,7 +73,6 @@ obj-$(CONFIG_ARCH_P3041) += p3041_serdes.o
 obj-$(CONFIG_ARCH_P4080) += p4080_serdes.o
 obj-$(CONFIG_ARCH_P5040) += p5040_serdes.o
 obj-$(CONFIG_ARCH_T4240) += t4240_serdes.o
-obj-$(CONFIG_ARCH_T4160) += t4240_serdes.o
 obj-$(CONFIG_ARCH_B4420) += b4860_serdes.o
 obj-$(CONFIG_ARCH_B4860) += b4860_serdes.o
 obj-$(CONFIG_ARCH_BSC9132) += bsc9132_serdes.o

diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 7d168e3c9a0e26970dbe541393f6cba88cdf80a8..3f2fc062b2b0719b90bc61d9c4baba52dbbfe321 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -527,8 +527,7 @@ static void fdt_fixup_usb(void *fdt)
 #define fdt_fixup_usb(x)
 #endif
 
-#if defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T4240) || \
-       defined(CONFIG_ARCH_T4160)
+#if defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T4240)
 void fdt_fixup_dma3(void *blob)
 {
        /* the 3rd DMA is not functional if SRIO2 is chosen */
@@ -545,7 +544,7 @@ void fdt_fixup_dma3(void *blob)
        case 0x29:
        case 0x2d:
        case 0x2e:
-#elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
+#elif defined(CONFIG_ARCH_T4240)
        u32 srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) &
                                    FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
        srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;

diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
index ee5015ec8f3ebb687dfea9b9edce269e1b2ff596..5bf0047930fef9ba65507e17fea5f47e49887877 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
@@ -392,7 +392,7 @@ const char *serdes_clock_to_string(u32 clock)
        case SRDS_PLLCR0_RFCK_SEL_161_13:
                return "161.1328123";
        default:
-#if defined(CONFIG_TARGET_T4240QDS) || defined(CONFIG_TARGET_T4160QDS)
+#if defined(CONFIG_TARGET_T4240QDS)
                return "???";
 #else
                return "122.88";

diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index e6e3f17bb272fddd17adffb0f1eb8fba8a44fd51..e229a5c5a7e0cc15901f70170728af52001729d9 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -126,8 +126,7 @@ void get_sys_info(sys_info_t *sys_info)
         * it uses 6.
         * T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0
         */
-#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) || \
-       defined(CONFIG_ARCH_T2080)
+#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T2080)
        svr = get_svr();
        switch (SVR_SOC_VER(svr)) {
        case SVR_T4240:

diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
index a8c0c47f4af1720d7c0971f3c00e9416956d1f01..61402e84ef62823726eb11bdd8be06d79ada5a83 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
@@ -262,208 +262,6 @@ static const struct serdes_config serdes4_cfg_tbl[] = {
        {18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}},
        {}
 };
-#elif defined(CONFIG_ARCH_T4160)
-static const struct serdes_config serdes1_cfg_tbl[] = {
-       /* SerDes 1 */
-       {1, {NONE, NONE, NONE, NONE,
-               XAUI_FM1_MAC10, XAUI_FM1_MAC10,
-               XAUI_FM1_MAC10, XAUI_FM1_MAC10} },
-       {2, {NONE, NONE, NONE, NONE,
-               HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
-               HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} },
-       {4, {NONE, NONE, NONE, NONE,
-               HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
-               HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} },
-       {27, {NONE, NONE, NONE, NONE,
-               SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
-               SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
-       {28, {NONE, NONE, NONE, NONE,
-               SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
-               SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
-       {35, {NONE, NONE, NONE, NONE,
-               SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
-               SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
-       {36, {NONE, NONE, NONE, NONE,
-               SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
-               SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
-       {37, {NONE, NONE, NONE, NONE,
-               NONE, NONE, QSGMII_FM1_A, NONE} },
-       {38, {NONE, NONE, NONE, NONE,
-               NONE, NONE, QSGMII_FM1_A, NONE} },
-       {}
-};
-static const struct serdes_config serdes2_cfg_tbl[] = {
-       /* SerDes 2 */
-       {6, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
-               XAUI_FM2_MAC9, XAUI_FM2_MAC9,
-               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
-               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
-       {7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
-               XAUI_FM2_MAC9, XAUI_FM2_MAC9,
-               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
-               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
-       {12, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
-               XAUI_FM2_MAC9, XAUI_FM2_MAC9,
-               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
-               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
-       {13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
-               XAUI_FM2_MAC9, XAUI_FM2_MAC9,
-               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
-               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
-       {15, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
-               HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
-               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
-               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
-       {16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
-               HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
-               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
-               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
-       {21, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
-               HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
-               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
-               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
-       {22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
-               HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
-               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
-               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
-       {24, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
-               HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
-               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
-               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
-       {25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
-               HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
-               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
-               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
-       {26, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
-               HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
-               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
-               NONE, NONE} },
-       {27, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
-               SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
-               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
-               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
-       {28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
-               SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
-               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
-               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
-       {35, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
-               SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
-               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
-               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
-       {36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
-               SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
-               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
-               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
-       {37, {NONE, NONE, QSGMII_FM2_B, NONE,
-               NONE, NONE, QSGMII_FM2_A, NONE} },
-       {38, {NONE, NONE, QSGMII_FM2_B, NONE,
-               NONE, NONE, QSGMII_FM2_A, NONE} },
-       {39, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
-               SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
-               NONE, NONE, QSGMII_FM2_A, NONE} },
-       {40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
-               SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
-               NONE, NONE, QSGMII_FM2_A, NONE} },
-       {45, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
-               SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
-               NONE, NONE, QSGMII_FM2_A, NONE} },
-       {46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
-               SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
-               NONE, NONE, QSGMII_FM2_A, NONE} },
-       {47, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
-               SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
-               NONE, NONE, QSGMII_FM2_A, NONE} },
-       {48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
-               SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
-               NONE, NONE, QSGMII_FM2_A, NONE} },
-       {49, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
-               XAUI_FM2_MAC9, XAUI_FM2_MAC9,
-               NONE, NONE, QSGMII_FM2_A, NONE} },
-       {50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
-               XAUI_FM2_MAC9, XAUI_FM2_MAC9,
-               NONE, NONE, QSGMII_FM2_A, NONE} },
-       {51, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
-               HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
-               NONE, NONE, QSGMII_FM2_A, NONE} },
-       {52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
-               HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
-               NONE, NONE, QSGMII_FM2_A, NONE} },
-       {53, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
-               HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
-               NONE, NONE, QSGMII_FM2_A, NONE} },
-       {54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
-               HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
-               NONE, NONE, QSGMII_FM2_A, NONE} },
-       {55, {NONE, XFI_FM1_MAC10,
-               XFI_FM2_MAC10, NONE,
-               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
-               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
-       {56, {NONE, XFI_FM1_MAC10,
-               XFI_FM2_MAC10, NONE,
-               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
-               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
-       {57, {NONE, XFI_FM1_MAC10,
-               XFI_FM2_MAC10, NONE,
-               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
-               NONE, NONE} },
-       {}
-};
-static const struct serdes_config serdes3_cfg_tbl[] = {
-       /* SerDes 3 */
-       {1, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
-       {2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
-       {3, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
-       {4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
-       {5, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
-       {6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
-       {7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
-       {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
-       {9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
-               INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} },
-       {10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
-               INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} },
-       {11, {NONE, NONE, NONE, NONE,
-               PCIE2, PCIE2, PCIE2, PCIE2} },
-       {12, {NONE, NONE, NONE, NONE,
-               PCIE2, PCIE2, PCIE2, PCIE2} },
-       {13, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
-               PCIE2, PCIE2, PCIE2, PCIE2} },
-       {14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
-               PCIE2, PCIE2, PCIE2, PCIE2} },
-       {15, {NONE, NONE, NONE, NONE,
-               SRIO1, SRIO1, SRIO1, SRIO1} },
-       {16, {NONE, NONE, NONE, NONE,
-               SRIO1, SRIO1, SRIO1, SRIO1} },
-       {17, {NONE, NONE, NONE, NONE,
-               SRIO1, SRIO1, SRIO1, SRIO1} },
-       {18, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
-               SRIO1, SRIO1, SRIO1, SRIO1} },
-       {19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
-               SRIO1, SRIO1, SRIO1, SRIO1} },
-       {20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
-               SRIO1, SRIO1, SRIO1, SRIO1} },
-       {}
-};
-static const struct serdes_config serdes4_cfg_tbl[] = {
-       /* SerDes 4 */
-       {3, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, PCIE4, PCIE4} },
-       {4, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, PCIE4, PCIE4} },
-       {5, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} },
-       {6, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} },
-       {7, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} },
-       {8, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} },
-       {9, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, SATA1, SATA2} },
-       {10, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, SATA1, SATA2} },
-       {11, {NONE, NONE, NONE, NONE, AURORA, AURORA, SATA1, SATA2} },
-       {12, {NONE, NONE, NONE, NONE, AURORA, AURORA, SATA1, SATA2} },
-       {13, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} },
-       {14, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} },
-       {15, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} },
-       {16, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} },
-       {18, {NONE, NONE, NONE, NONE, AURORA, AURORA, AURORA, AURORA} },
-       {}
-}
-;
 #else
 #error "Need to define SerDes protocol"
 #endif

diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 33a3b3a13db7249823b6019fdf882762806ee730..cfe74bcb84a2c58005f7710df8bc5a2253dbf517 100644 (file)
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -184,7 +184,7 @@
 #define CONFIG_SYS_FSL_PCIE_COMPAT     "fsl,qoriq-pcie-v2.2"
 #define CONFIG_ESDHC_HC_BLK_ADDR
 
-#elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
+#elif defined(CONFIG_ARCH_T4240)
 #define CONFIG_FSL_CORENET             /* Freescale CoreNet platform */
 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
 #define CONFIG_SYS_FSL_QMAN_V3         /* QMAN version 3 */
@@ -199,9 +199,6 @@
 #define CONFIG_SYS_NUM_FM1_10GEC       1
 #define CONFIG_SYS_NUM_FM2_DTSEC       8
 #define CONFIG_SYS_NUM_FM2_10GEC       1
-#if defined(CONFIG_ARCH_T4160)
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS  { 1, 1 }
-#endif
 #endif
 #define CONFIG_SYS_FSL_NUM_CC_PLLS     5
 #define CONFIG_SYS_FSL_SRDS_1

diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h
index 991d75312a34d2c94cffac6bc9b5c70f44c839e6..3a1d858ec6456a0afcdd10d0b2a20d7f08ec8d2a 100644 (file)
--- a/arch/powerpc/include/asm/fsl_secure_boot.h
+++ b/arch/powerpc/include/asm/fsl_secure_boot.h
@@ -21,7 +21,6 @@
 
 #if defined(CONFIG_TARGET_B4860QDS) || \
        defined(CONFIG_TARGET_B4420QDS) || \
-       defined(CONFIG_TARGET_T4160QDS) || \
        defined(CONFIG_TARGET_T4240QDS) || \
        defined(CONFIG_TARGET_T2080QDS) || \
        defined(CONFIG_TARGET_T2080RDB) || \

diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 70112c91fc51e09962bd001e053d4f47bc1885db..f539c0be71ed763b96e220eff997e6bca73e546e 100644 (file)
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1757,7 +1757,7 @@ typedef struct ccsr_gur {
 /* use reserved bits 18~23 as scratch space to host DDR PLL ratio */
 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT      8
 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK    0x3f
-#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
+#if defined(CONFIG_ARCH_T4240)
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL                0xfc000000
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT  26
 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL                0x00fe0000
@@ -1869,7 +1869,7 @@ typedef struct ccsr_gur {
 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII          0x00100000
 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE         0x00180000
 #endif
-#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
+#if defined(CONFIG_ARCH_T4240)
 #define FSL_CORENET_RCWSR13_EC1                        0x60000000 /* bits 417..418 */
 #define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII       0x00000000
 #define FSL_CORENET_RCWSR13_EC1_FM2_GPIO               0x40000000

diff --git a/board/freescale/t4rdb/Kconfig b/board/freescale/t4rdb/Kconfig
index a94a57e7feebd013a10fa552fdc101f54eb76d7e..542e574fed142b341b05104785ab1f0f4c115981 100644 (file)
--- a/board/freescale/t4rdb/Kconfig
+++ b/board/freescale/t4rdb/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_T4160RDB || TARGET_T4240RDB
+if TARGET_T4240RDB
 
 config SYS_BOARD
        default "t4rdb"

diff --git a/board/freescale/t4rdb/MAINTAINERS b/board/freescale/t4rdb/MAINTAINERS
index 7380408aaec33557e761f32f471453e826acbc71..844a15259c0288f42c52847009d0b6dddc92b044 100644 (file)
--- a/board/freescale/t4rdb/MAINTAINERS
+++ b/board/freescale/t4rdb/MAINTAINERS
@@ -3,6 +3,5 @@ M:      Priyanka Jain <priyanka.jain@nxp.com>
 S:     Maintained
 F:     board/freescale/t4rdb/
 F:     include/configs/T4240RDB.h
-F:     configs/T4160RDB_defconfig
 F:     configs/T4240RDB_defconfig
 F:     configs/T4240RDB_SDCARD_defconfig

diff --git a/board/freescale/t4rdb/Makefile b/board/freescale/t4rdb/Makefile
index 209983a24bd1d12c4b14d8dc602a601fe7310bc8..f1fd623339cb7f84fd00f0f104b3d522fcc5af9b 100644 (file)
--- a/board/freescale/t4rdb/Makefile
+++ b/board/freescale/t4rdb/Makefile
@@ -7,7 +7,6 @@
 ifdef CONFIG_SPL_BUILD
 obj-y  += spl.o
 else
-obj-$(CONFIG_TARGET_T4160RDB)  += t4240rdb.o
 obj-$(CONFIG_TARGET_T4240RDB)  += t4240rdb.o
 obj-y                  += cpld.o
 obj-y                  += eth.o

diff --git a/configs/T4160RDB_defconfig b/configs/T4160RDB_defconfig
deleted file mode 100644 (file)
index 706d6a2..0000000
--- a/configs/T4160RDB_defconfig
+++ /dev/null
@@ -1,57 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T4160RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_CORTINA=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
-CONFIG_OF_LIBFDT=y

diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig
index e6a51f560978e4fd52daf547b515601f6c7ce623..8246f627982c1ff27ad5c011ed2192e2bbd03dbe 100644 (file)
--- a/drivers/ddr/fsl/Kconfig
+++ b/drivers/ddr/fsl/Kconfig
@@ -44,8 +44,7 @@ config SYS_NUM_DDR_CTLRS
                        ARCH_P4080      || \
                        ARCH_P5040      || \
                        ARCH_LX2160A    || \
-                       ARCH_LX2162A    || \
-                       ARCH_T4160
+                       ARCH_LX2162A
        default 1
 
 config SYS_FSL_DDR_VER

diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index a0010a17de97a776fd24ab396685f0fb85d17163..483401681d8a9ace5bebdf5c8ea339a73baf2e62 100644 (file)
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -738,7 +738,6 @@ config SYS_DPAA_QBMAN
                     ARCH_T1042 || \
                     ARCH_T2080 || \
                     ARCH_T4240 || \
-                    ARCH_T4160 || \
                     ARCH_P4080 || \
                     ARCH_P3041 || \
                     ARCH_P5040 || \

diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile
index c988e4e9257febb17bc64421ca6fa6980fc66482..ae3841217663f20a2141ebf56805b42daaf4f1bd 100644 (file)
--- a/drivers/net/fm/Makefile
+++ b/drivers/net/fm/Makefile
@@ -26,7 +26,6 @@ obj-$(CONFIG_ARCH_T1042)      += t1040.o
 obj-$(CONFIG_ARCH_T1024) += t1024.o
 obj-$(CONFIG_ARCH_T2080) += t2080.o
 obj-$(CONFIG_ARCH_T4240) += t4240.o
-obj-$(CONFIG_ARCH_T4160) += t4240.o
 obj-$(CONFIG_ARCH_B4420) += b4860.o
 obj-$(CONFIG_ARCH_B4860) += b4860.o
 obj-$(CONFIG_ARCH_LS1043A)     += ls1043.o