net: smc911x: Determine bus width at runtime

The SMC911x Ethernet MACs can be integrated using a 16 or 32-bit bus.
The driver needs to know about this choice, which is the reason for us
having a Kconfig symbol for that.

Now this bus width is already described using a devicetree property, and
since the driver is DM compliant and is using the DT now, we should query
this at runtime. We leave the Kconfig choice around, in case the DT is
missing this property.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>

diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
index d596d96f4b30f3a28d4ecb4b5941d71c015da618..3afebee440220b93e85dd1974ed51bcc116b436a 100644 (file)
--- a/drivers/net/smc911x.c
+++ b/drivers/net/smc911x.c
@@ -28,6 +28,7 @@ struct smc911x_priv {
        phys_addr_t             iobase;
        const struct chip_id    *chipid;
        unsigned char           enetaddr[6];
+       bool                    use_32_bit_io;
 };
 
 static const struct chip_id chip_ids[] =  {
@@ -48,28 +49,24 @@ static const struct chip_id chip_ids[] =  {
 
 #define DRIVERNAME "smc911x"
 
-#if defined (CONFIG_SMC911X_32_BIT)
 static u32 smc911x_reg_read(struct smc911x_priv *priv, u32 offset)
 {
-       return readl(priv->iobase + offset);
-}
+       if (priv->use_32_bit_io)
+               return readl(priv->iobase + offset);
 
-static void smc911x_reg_write(struct smc911x_priv *priv, u32 offset, u32 val)
-{
-       writel(val, priv->iobase + offset);
-}
-#else
-static u32 smc911x_reg_read(struct smc911x_priv *priv, u32 offset)
-{
        return (readw(priv->iobase + offset) & 0xffff) |
               (readw(priv->iobase + offset + 2) << 16);
 }
+
 static void smc911x_reg_write(struct smc911x_priv *priv, u32 offset, u32 val)
 {
-       writew(val & 0xffff, priv->iobase + offset);
-       writew(val >> 16, priv->iobase + offset + 2);
+       if (priv->use_32_bit_io) {
+               writel(val, priv->iobase + offset);
+       } else {
+               writew(val & 0xffff, priv->iobase + offset);
+               writew(val >> 16, priv->iobase + offset + 2);
+       }
 }
-#endif /* CONFIG_SMC911X_32_BIT */
 
 static u32 smc911x_get_mac_csr(struct smc911x_priv *priv, u8 reg)
 {
@@ -493,6 +490,8 @@ int smc911x_initialize(u8 dev_num, int base_addr)
        priv->iobase = base_addr;
        priv->dev.iobase = base_addr;
 
+       priv->use_32_bit_io = CONFIG_IS_ENABLED(SMC911X_32_BIT);
+
        /* Try to detect chip. Will fail if not present. */
        ret = smc911x_detect_chip(priv);
        if (ret) {
@@ -603,10 +602,18 @@ static int smc911x_of_to_plat(struct udevice *dev)
 {
        struct smc911x_priv *priv = dev_get_priv(dev);
        struct eth_pdata *pdata = dev_get_plat(dev);
+       u32 io_width;
+       int ret;
 
        pdata->iobase = dev_read_addr(dev);
        priv->iobase = pdata->iobase;
 
+       ret = dev_read_u32(dev, "reg-io-width", &io_width);
+       if (!ret)
+               priv->use_32_bit_io = (io_width == 4);
+       else
+               priv->use_32_bit_io = CONFIG_IS_ENABLED(SMC911X_32_BIT);
+
        return 0;
 }