]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
lpc32xx: Kconfig: switch to CONFIG_CONS_INDEX
authorTrevor Woerner <twoerner@gmail.com>
Fri, 11 Jun 2021 02:37:02 +0000 (22:37 -0400)
committerTom Rini <trini@konsulko.com>
Tue, 6 Jul 2021 18:11:50 +0000 (14:11 -0400)
There's nothing special or unique to the lpc32xx that requires its own config
parameter for specifying the console uart index. Therefore instead of using
the lpc32xx-specific CONFIG_SYS_LPC32XX_UART include parameter, use the
already-available CONFIG_CONS_INDEX from Kconfig.

Signed-off-by: Trevor Woerner <twoerner@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
arch/arm/include/asm/arch-lpc32xx/config.h
arch/arm/mach-lpc32xx/devices.c
board/timll/devkit3250/devkit3250.c
board/timll/devkit3250/devkit3250_spl.c
board/work-microwave/work_92105/work_92105.c
board/work-microwave/work_92105/work_92105_spl.c
configs/devkit3250_defconfig
configs/work_92105_defconfig
include/configs/devkit3250.h
include/configs/work_92105.h
scripts/config_whitelist.txt

index 0836091af244c953676c10be27ce9cacd33e38fc..45e46f99463eed9d4c5e00a1ee1095d0f7b1f85c 100644 (file)
@@ -12,8 +12,8 @@
 /* Basic CPU architecture */
 
 /* UART configuration */
-#if    (CONFIG_SYS_LPC32XX_UART == 1) || (CONFIG_SYS_LPC32XX_UART == 2) || \
-       (CONFIG_SYS_LPC32XX_UART == 7)
+#if    (CONFIG_CONS_INDEX == 1) || (CONFIG_CONS_INDEX == 2) || \
+       (CONFIG_CONS_INDEX == 7)
 #if !defined(CONFIG_LPC32XX_HSUART)
 #define CONFIG_LPC32XX_HSUART
 #endif
index e1e2e0d09497e664a00778329edc608a3ebe87e1..0a4fef295a36b84605f0de249643de64a7796cb8 100644 (file)
@@ -23,8 +23,7 @@ void lpc32xx_uart_init(unsigned int uart_id)
                return;
 
        /* Disable loopback mode, if it is set by S1L bootloader */
-       clrbits_le32(&ctrl->loop,
-                    UART_LOOPBACK(CONFIG_SYS_LPC32XX_UART));
+       clrbits_le32(&ctrl->loop, UART_LOOPBACK(uart_id));
 
        if (uart_id < 3 || uart_id > 6)
                return;
index 3c744b943f40fa1362af07c60bc709b2b6ac7084..9d4ffb0f979b577ca58ef6e8d2012b93fbac4f8c 100644 (file)
@@ -38,7 +38,7 @@ void reset_periph(void)
 
 int board_early_init_f(void)
 {
-       lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART);
+       lpc32xx_uart_init(CONFIG_CONS_INDEX);
        lpc32xx_i2c_init(1);
        lpc32xx_i2c_init(2);
        lpc32xx_ssp_init();
index 47af78ae0b1d6a7870c6bcdea94b27e34e8a6f7c..12e8ae9c39cb9e20104c4f71f09dede8c4b9208c 100644 (file)
@@ -49,7 +49,7 @@ void spl_board_init(void)
        /* First of all silence buzzer controlled by GPO_20 */
        writel((1 << 20), &gpio->p3_outp_clr);
 
-       lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART);
+       lpc32xx_uart_init(CONFIG_CONS_INDEX);
        preloader_console_init();
 
        ddr_init(&dram_64mb);
index bdcecff7308ff442e0a7739d51202ffa7b0936f7..5d12f84cfeaaedb8285238f64bac439320e507ea 100644 (file)
@@ -37,7 +37,7 @@ void reset_periph(void)
 int board_early_init_f(void)
 {
        /* initialize serial port for console */
-       lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART);
+       lpc32xx_uart_init(CONFIG_CONS_INDEX);
        /* enable I2C, SSP, MAC, NAND */
        lpc32xx_i2c_init(1); /* only I2C1 has devices, I2C2 has none */
        lpc32xx_ssp_init();
index a31553a2d25b5271eb5a73744f404cc93039b7d8..d9401145f27d2cb444971aa89c3ea9feefb2bf78 100644 (file)
@@ -58,7 +58,7 @@ const struct emc_dram_settings dram_128mb = {
 void spl_board_init(void)
 {
        /* initialize serial port for console */
-       lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART);
+       lpc32xx_uart_init(CONFIG_CONS_INDEX);
        /* initialize console */
        preloader_console_init();
        /* init DDR and NAND to chainload U-Boot */
index 93c048cee86b8cd5aa7e7576aea771c0b0265278..9ae70f7d463466fe607b123d1b40961398ecd59a 100644 (file)
@@ -51,6 +51,8 @@ CONFIG_PHYLIB=y
 CONFIG_PHY_ADDR_ENABLE=y
 CONFIG_PHY_ADDR=31
 CONFIG_PHY_SMSC=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_CONS_INDEX=5
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_USB=y
index c3f666dcfe91a9a7f2573aca94d43777c19c6cf8..e9605adeddfa5babf9bfb9b12820b57cdb7458fe 100644 (file)
@@ -48,5 +48,7 @@ CONFIG_MTD_RAW_NAND=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_ADDR_ENABLE=y
 CONFIG_PHY_SMSC=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_CONS_INDEX=5
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
index 5d2b77b4a372a7123e4cb22fcf0128bcd5aa64b0..921a38c01ea7170fe1d5d3f0a0185762e57b6b73 100644 (file)
 #define CONFIG_SYS_INIT_SP_ADDR                (CONFIG_SYS_SDRAM_BASE + SZ_4K \
                                         - GENERATED_GBL_DATA_SIZE)
 
-/*
- * Serial Driver
- */
-#define CONFIG_SYS_LPC32XX_UART                5   /* UART5 */
-
 /*
  * DMA
  */
index 7874b77f3f88b12facc043529007724eed3dc19c..076a1b065ebc63734c68aa9732da33665aaac391 100644 (file)
 #define CONFIG_SYS_INIT_SP_ADDR                (CONFIG_SYS_SDRAM_BASE + SZ_512K \
                                         - GENERATED_GBL_DATA_SIZE)
 
-/*
- * Serial Driver
- */
-#define CONFIG_SYS_LPC32XX_UART                5   /* UART5 - NS16550 */
-
 /*
  * Ethernet Driver
  */
index e549a5557f5f854df0d2bf70e9962a22b255fbf3..624d851f0dd20252c9077e7038d50382de24a1a2 100644 (file)
@@ -2734,7 +2734,6 @@ CONFIG_SYS_LOW
 CONFIG_SYS_LOWMEM_BASE
 CONFIG_SYS_LOW_RES_TIMER
 CONFIG_SYS_LPAE_SDRAM_BASE
-CONFIG_SYS_LPC32XX_UART
 CONFIG_SYS_LS1_DDR_BLOCK1_SIZE
 CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH
 CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS