#define EXYNOS4412_FIXED_CIU_CLK_DIV 4
+/* Quirks */
+#define DWMCI_QUIRK_DISABLE_SMU BIT(0)
+
#ifdef CONFIG_DM_MMC
#include <dm.h>
DECLARE_GLOBAL_DATA_PTR;
struct exynos_dwmmc_variant {
u32 clksel; /* CLKSEL register offset */
u8 div; /* (optional) fixed clock divider value: 0..7 */
+ u32 quirks; /* quirk flags - see DWMCI_QUIRK_... */
};
/* Exynos implmentation specific drver private data */
{
struct dwmci_exynos_priv_data *priv = exynos_dwmmc_get_priv(host);
- if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) {
+ if (priv->chip->quirks & DWMCI_QUIRK_DISABLE_SMU) {
dwmci_writel(host, EMMCP_MPSBEGIN0, 0);
dwmci_writel(host, EMMCP_SEND0, 0);
dwmci_writel(host, EMMCP_CTRL0,
}
host->name = "EXYNOS DWMMC";
-#ifdef CONFIG_EXYNOS5420
- host->quirks = DWMCI_QUIRK_DISABLE_SMU;
-#endif
host->board_init = exynos_dwmci_board_init;
-
host->caps = MMC_MODE_DDR_52MHz;
host->clksel = exynos_dwmci_clksel;
host->get_mmc_clk = exynos_dwmci_get_clk;
static const struct exynos_dwmmc_variant exynos5_drv_data = {
.clksel = DWMCI_CLKSEL,
+#ifdef CONFIG_EXYNOS5420
+ .quirks = DWMCI_QUIRK_DISABLE_SMU,
+#endif
};
static const struct udevice_id exynos_dwmmc_ids[] = {
#define DWMCI_IDINTEN_TI BIT(0)
#define DWMCI_IDINTEN_MASK (DWMCI_IDINTEN_TI | DWMCI_IDINTEN_RI)
-/* Quirks */
-#define DWMCI_QUIRK_DISABLE_SMU BIT(0)
-
/**
* struct dwmci_idmac_regs - Offsets of IDMAC registers
*
*
* @name: Device name
* @ioaddr: Base I/O address of controller
- * @quirks: Quick flags - see DWMCI_QUIRK_...
* @caps: Capabilities - see MMC_MODE_...
* @clock: Current clock frequency (after internal divider), Hz
* @bus_hz: Bus speed in Hz, if @get_mmc_clk() is NULL
struct dwmci_host {
const char *name;
void *ioaddr;
- unsigned int quirks;
unsigned int caps;
unsigned int clock;
unsigned int bus_hz;