prompt "Target select"
optional
-config TARGET_MPC832XEMDS
- bool "Support MPC832XEMDS"
- select ARCH_MPC832X
- select BOARD_EARLY_INIT_F
-
config TARGET_MPC8349EMDS
bool "Support MPC8349EMDS"
select ARCH_MPC8349
config FSL_ELBC
bool
-source "board/freescale/mpc832xemds/Kconfig"
source "board/freescale/mpc8349emds/Kconfig"
source "board/freescale/mpc837xerdb/Kconfig"
source "board/ids/ids8313/Kconfig"
i2c_write(0x26, 0x6, 1, &val8, 1);
val8 = 0x34;
i2c_write(0x26, 0x7, 1, &val8, 1);
-#if defined(CONFIG_TARGET_MPC832XEMDS)
- val8 = 0xf9; /* PMC2, PMC3 slot to PCI bus */
-#else
val8 = 0xf3; /* PMC1, PMC2, PMC3 slot to PCI bus */
-#endif
i2c_write(0x26, 0x2, 1, &val8, 1);
val8 = 0xff;
i2c_write(0x26, 0x3, 1, &val8, 1);
eieio();
-#if defined(CONFIG_TARGET_MPC832XEMDS)
- printf("PCI 32bit bus on PMC2 &PMC3\n");
-#else
printf("PCI 32bit bus on PMC1 & PMC2 &PMC3\n");
#endif
-#endif
-
-#if defined(CONFIG_PQ_MDS_PIB_ATM)
-#if defined(CONFIG_TARGET_MPC832XEMDS)
- val8 = 0;
- i2c_write(0x26, 0x7, 1, &val8, 1);
- val8 = 0xf7;
- i2c_write(0x26, 0x3, 1, &val8, 1);
-
- val8 = 0;
- i2c_write(0x21, 0x6, 1, &val8, 1);
- i2c_write(0x21, 0x7, 1, &val8, 1);
-
- val8 = 0xdf;
- i2c_write(0x21, 0x2, 1, &val8, 1);
- val8 = 0xef;
- i2c_write(0x21, 0x3, 1, &val8, 1);
- eieio();
-
- printf("QOC3 ATM card on PMC1\n");
-#endif
-#endif
/* Reset to original I2C bus */
i2c_set_bus_num(orig_i2c_bus);
return 0;
+++ /dev/null
-if TARGET_MPC832XEMDS
-
-config SYS_BOARD
- default "mpc832xemds"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "MPC832XEMDS"
-
-endif
+++ /dev/null
-MPC832XEMDS BOARD
-#M: Dave Liu <daveliu@freescale.com>
-S: Orphan (since 2018-05)
-F: board/freescale/mpc832xemds/
-F: include/configs/MPC832XEMDS.h
-F: configs/MPC832XEMDS_defconfig
-F: configs/MPC832XEMDS_ATM_defconfig
-F: configs/MPC832XEMDS_HOST_33_defconfig
-F: configs/MPC832XEMDS_HOST_66_defconfig
-F: configs/MPC832XEMDS_SLAVE_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y += mpc832xemds.o
-obj-$(CONFIG_PCI) += pci.o
+++ /dev/null
-Freescale MPC832XEMDS Board
------------------------------------------
-1. Board Switches and Jumpers
-1.0 There are five Dual-In-Line Packages(DIP) Switches on MPC832XE SYS board
- For some reason, the HW designers describe the switch settings
- in terms of 0 and 1, and then map that to physical switches where
- the label "On" refers to logic 0 and "Off" is logic 1.
-
- Switch bits are numbered 1 through, like, 4 6 8 or 10, but the
- bits may contribute to signals that are numbered based at 0,
- and some of those signals may be high-bit-number-0 too. Heed
- well the names and labels and do not get confused.
-
- "Off" == 1
- "On" == 0
-
- SW3 is switch 18 as silk-screened onto the board.
- SW4[8] is the bit labeled 8 on Switch 4.
- SW5[1:6] refers to bits labeled 1 through 6 in order on switch 5.
- SW6[7:1] refers to bits labeled 7 through 1 in order on switch 6.
- SW7[1:8]= 0000_0001 refers to bits labeled 1 through 6 is set as "On"
- and bits labeled 8 is set as "Off".
-
-1.1 For the MPC832XEMDS PROTO Board
-
- First, make sure the board default setting is consistent with the document
- shipped with your board. Then apply the following setting:
- SW3[1-8]= 0000_1000 (core PLL setting, core enable)
- SW4[1-8]= 0001_0010 (Flash boot on local bus, system PLL setting)
- SW5[1-8]= 0010_0110 (Boot from high end)
- SW6[1-8]= 0011_0100 (Flash boot on 16 bit local bus)
- SW7[1-8]= 1000_0011 (QE PLL setting)
-
- ENET3/4 MII mode settings:
- J1 1-2 (ETH3_TXER)
- J2 2-3 (MII mode)
- J3 2-3 (MII mode)
- J4 2-3 (ADSL clockOscillator)
- J5 1-2 (ETH4_TXER)
- J6 2-3 (ClockOscillator)
- JP1 removed (don't force PORESET)
- JP2 mounted (ETH4/2 MII)
- JP3 mounted (ETH3 MII)
- JP4 mounted (HRCW from BCSR)
-
- ENET3/4 RMII mode settings:
- J1 1-2 (ETH3_TXER)
- J2 1-2 (RMII mode)
- J3 1-2 (RMII mode)
- J4 2-3 (ADSL clockOscillator)
- J5 1-2 (ETH4_TXER)
- J6 2-3 (ClockOscillator)
- JP1 removed (don't force PORESET)
- JP2 removed (ETH4/2 RMII)
- JP3 removed (ETH3 RMII)
- JP4 removed (HRCW from FLASH)
-
- on board Oscillator: 66M
-
-
-2. Memory Map
-
-2.1 The memory map should look pretty much like this:
-
- 0x0000_0000 0x7fff_ffff DDR 2G
- 0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M
- 0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M
- 0xc000_0000 0xdfff_ffff Empty 512M
- 0xe000_0000 0xe01f_ffff Int Mem Reg Space 2M
- 0xe020_0000 0xe02f_ffff Empty 1M
- 0xe030_0000 0xe03f_ffff PCI IO 1M
- 0xe040_0000 0xefff_ffff Empty 252M
- 0xf400_0000 0xf7ff_ffff Empty 64M
- 0xf800_0000 0xf800_7fff BCSR on CS1 32K
- 0xf800_8000 0xf800_ffff PIB CS2 32K
- 0xf801_0000 0xf801_7fff PIB CS3 32K
- 0xfe00_0000 0xfeff_ffff FLASH on CS0 16M
-
-
-3. Definitions
-
-3.1 Explanation of NEW definitions in:
-
- include/configs/MPC832XEPB.h
-
- CONFIG_MPC83xx MPC83xx family for MPC8349, MPC8360 and MPC832x
- CONFIG_MPC832x MPC832x specific
- CONFIG_MPC832XEMDS MPC832XEMDS board specific
-
-4. Compilation
-
- Assuming you're using BASH shell:
-
- export CROSS_COMPILE=your-cross-compile-prefix
- cd u-boot
- make distclean
- make MPC832XEMDS_config
- make
-
- MPC832x support PCI 33MHz and PCI 66MHz, to make U-Boot support PCI:
-
- 1)Make sure the DIP SW support PCI mode as described in Section 1.1.
-
- 2)To Make U-Boot image support PCI 33MHz, use
- Make MPC832XEMDS_HOST_33_config
-
- 3)To Make U-Boot image support PCI 66MHz, use
- Make MPC832XEMDS_HOST_66M_config
-
-5. Downloading and Flashing Images
-
-5.0 Download over network:
-
- tftp 10000 u-boot.bin
-
-5.1 Reflash U-Boot Image using U-Boot
-
- tftp 20000 u-boot.bin
- protect off fe000000 fe0fffff
- erase fe000000 fe0fffff
- cp.b 20000 fe000000 xxxx
-
-You have to supply the correct byte count with 'xxxx' from the TFTP result log.
-Maybe 3ffff will work too, that corresponds to the erased sectors.
-
-
-6. Notes
- 1) The console baudrate for MPC832XEMDS is 115200bps.
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
- *
- * Dave Liu <daveliu@freescale.com>
- */
-
-#include <common.h>
-#include <fdt_support.h>
-#include <init.h>
-#include <ioports.h>
-#include <mpc83xx.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <command.h>
-#if defined(CONFIG_PCI)
-#include <pci.h>
-#endif
-#include <asm/global_data.h>
-#include <asm/mmu.h>
-#if defined(CONFIG_OF_LIBFDT)
-#include <linux/libfdt.h>
-#endif
-#if defined(CONFIG_PQ_MDS_PIB)
-#include "../common/pq-mds-pib.h"
-#endif
-#include <linux/delay.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-const qe_iop_conf_t qe_iop_conf_tab[] = {
- /* ETH3 */
- {1, 0, 1, 0, 1}, /* TxD0 */
- {1, 1, 1, 0, 1}, /* TxD1 */
- {1, 2, 1, 0, 1}, /* TxD2 */
- {1, 3, 1, 0, 1}, /* TxD3 */
- {1, 9, 1, 0, 1}, /* TxER */
- {1, 12, 1, 0, 1}, /* TxEN */
- {3, 24, 2, 0, 1}, /* TxCLK->CLK10 */
-
- {1, 4, 2, 0, 1}, /* RxD0 */
- {1, 5, 2, 0, 1}, /* RxD1 */
- {1, 6, 2, 0, 1}, /* RxD2 */
- {1, 7, 2, 0, 1}, /* RxD3 */
- {1, 8, 2, 0, 1}, /* RxER */
- {1, 10, 2, 0, 1}, /* RxDV */
- {0, 13, 2, 0, 1}, /* RxCLK->CLK9 */
- {1, 11, 2, 0, 1}, /* COL */
- {1, 13, 2, 0, 1}, /* CRS */
-
- /* ETH4 */
- {1, 18, 1, 0, 1}, /* TxD0 */
- {1, 19, 1, 0, 1}, /* TxD1 */
- {1, 20, 1, 0, 1}, /* TxD2 */
- {1, 21, 1, 0, 1}, /* TxD3 */
- {1, 27, 1, 0, 1}, /* TxER */
- {1, 30, 1, 0, 1}, /* TxEN */
- {3, 6, 2, 0, 1}, /* TxCLK->CLK8 */
-
- {1, 22, 2, 0, 1}, /* RxD0 */
- {1, 23, 2, 0, 1}, /* RxD1 */
- {1, 24, 2, 0, 1}, /* RxD2 */
- {1, 25, 2, 0, 1}, /* RxD3 */
- {1, 26, 1, 0, 1}, /* RxER */
- {1, 28, 2, 0, 1}, /* Rx_DV */
- {3, 31, 2, 0, 1}, /* RxCLK->CLK7 */
- {1, 29, 2, 0, 1}, /* COL */
- {1, 31, 2, 0, 1}, /* CRS */
-
- {3, 4, 3, 0, 2}, /* MDIO */
- {3, 5, 1, 0, 2}, /* MDC */
-
- {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
-};
-
-int board_early_init_f(void)
-{
- volatile u8 *bcsr = (volatile u8 *)CONFIG_SYS_BCSR;
-
- /* Enable flash write */
- bcsr[9] &= ~0x08;
-
- return 0;
-}
-
-int board_early_init_r(void)
-{
-#ifdef CONFIG_PQ_MDS_PIB
- pib_init();
-#endif
- return 0;
-}
-
-int fixed_sdram(void);
-
-int dram_init(void)
-{
- volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- u32 msize = 0;
-
- if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
- return -ENXIO;
-
- /* DDR SDRAM - Main SODIMM */
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
-
- msize = fixed_sdram();
-
- /* set total bus SDRAM size(bytes) -- DDR */
- gd->ram_size = msize * 1024 * 1024;
-
- return 0;
-}
-
-/*************************************************************************
- * fixed sdram init -- doesn't use serial presence detect.
- ************************************************************************/
-int fixed_sdram(void)
-{
- volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- u32 msize = 0;
- u32 ddr_size;
- u32 ddr_size_log2;
-
- msize = CONFIG_SYS_DDR_SIZE;
- for (ddr_size = msize << 20, ddr_size_log2 = 0;
- (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
- if (ddr_size & 1) {
- return -1;
- }
- }
- im->sysconf.ddrlaw[0].ar =
- LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
-#if (CONFIG_SYS_DDR_SIZE != 128)
-#warning Currenly any ddr size other than 128 is not supported
-#endif
- im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
- im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
- im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
- im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
- im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
- im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
- im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
- im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
- im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
- im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
- im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
- im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
- __asm__ __volatile__ ("sync");
- udelay(200);
-
- im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
- __asm__ __volatile__ ("sync");
- return msize;
-}
-
-int checkboard(void)
-{
- puts("Board: Freescale MPC832XEMDS\n");
- return 0;
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI
- ft_pci_setup(blob, bd);
-#endif
-
- return 0;
-}
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
- */
-
-/*
- * PCI Configuration space access support for MPC83xx PCI Bridge
- */
-#include <init.h>
-#include <asm/mmu.h>
-#include <asm/io.h>
-#include <common.h>
-#include <mpc83xx.h>
-#include <pci.h>
-#include <i2c.h>
-#include <asm/fsl_i2c.h>
-#include <linux/delay.h>
-#include "../common/pq-mds-pib.h"
-
-static struct pci_region pci1_regions[] = {
- {
- bus_start: CONFIG_SYS_PCI1_MEM_BASE,
- phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
- size: CONFIG_SYS_PCI1_MEM_SIZE,
- flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
- },
- {
- bus_start: CONFIG_SYS_PCI1_IO_BASE,
- phys_start: CONFIG_SYS_PCI1_IO_PHYS,
- size: CONFIG_SYS_PCI1_IO_SIZE,
- flags: PCI_REGION_IO
- },
- {
- bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
- phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
- size: CONFIG_SYS_PCI1_MMIO_SIZE,
- flags: PCI_REGION_MEM
- },
-};
-
-#ifdef CONFIG_MPC83XX_PCI2
-static struct pci_region pci2_regions[] = {
- {
- bus_start: CONFIG_SYS_PCI2_MEM_BASE,
- phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
- size: CONFIG_SYS_PCI2_MEM_SIZE,
- flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
- },
- {
- bus_start: CONFIG_SYS_PCI2_IO_BASE,
- phys_start: CONFIG_SYS_PCI2_IO_PHYS,
- size: CONFIG_SYS_PCI2_IO_SIZE,
- flags: PCI_REGION_IO
- },
- {
- bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
- phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
- size: CONFIG_SYS_PCI2_MMIO_SIZE,
- flags: PCI_REGION_MEM
- },
-};
-#endif
-
-void pci_init_board(void)
-#ifdef CONFIG_PCISLAVE
-{
- volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
- volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
- volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0];
- struct pci_region *reg[] = { pci1_regions };
-
- /* Configure PCI Local Access Windows */
- pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
- pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
-
- pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
- pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
-
- mpc83xx_pci_init(1, reg);
-
- /*
- * Configure PCI Inbound Translation Windows
- */
- pci_ctrl[0].pitar0 = 0x0;
- pci_ctrl[0].pibar0 = 0x0;
- pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP |
- PIWAR_WTT_SNOOP | PIWAR_IWS_4K;
-
- pci_ctrl[0].pitar1 = 0x0;
- pci_ctrl[0].pibar1 = 0x0;
- pci_ctrl[0].piebar1 = 0x0;
- pci_ctrl[0].piwar1 &= ~PIWAR_EN;
-
- pci_ctrl[0].pitar2 = 0x0;
- pci_ctrl[0].pibar2 = 0x0;
- pci_ctrl[0].piebar2 = 0x0;
- pci_ctrl[0].piwar2 &= ~PIWAR_EN;
-
- /* Unlock the configuration bit */
- mpc83xx_pcislave_unlock(0);
- printf("PCI: Agent mode enabled\n");
-}
-#else
-{
- volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
- volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
- volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
-#ifndef CONFIG_MPC83XX_PCI2
- struct pci_region *reg[] = { pci1_regions };
-#else
- struct pci_region *reg[] = { pci1_regions, pci2_regions };
-#endif
-
- /* initialize the PCA9555PW IO expander on the PIB board */
- pib_init();
-
-#if defined(CONFIG_PCI_66M)
- clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
- printf("PCI clock is 66MHz\n");
-#elif defined(CONFIG_PCI_33M)
- clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 |
- OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR;
- printf("PCI clock is 33MHz\n");
-#else
- clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
- printf("PCI clock is 66MHz\n");
-#endif
- udelay(2000);
-
- /* Configure PCI Local Access Windows */
- pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
- pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
-
- pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
- pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;
-
- udelay(2000);
-
-#ifndef CONFIG_MPC83XX_PCI2
- mpc83xx_pci_init(1, reg);
-#else
- mpc83xx_pci_init(2, reg);
-#endif
-}
-#endif /* CONFIG_PCISLAVE */
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFE000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_CLK_FREQ=66000000
-CONFIG_MPC83xx=y
-CONFIG_HIGH_BATS=y
-CONFIG_TARGET_MPC832XEMDS=y
-CONFIG_CORE_PLL_RATIO_2_1=y
-CONFIG_QUICC_MULT_FACTOR_3=y
-CONFIG_PCI_HOST_MODE_ENABLE=y
-CONFIG_PCI_INT_ARBITER1_ENABLE=y
-CONFIG_BOOT_MEMORY_SPACE_LOW=y
-CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
-CONFIG_BAT0=y
-CONFIG_BAT0_NAME="SDRAM"
-CONFIG_BAT0_BASE=0x00000000
-CONFIG_BAT0_LENGTH_256_MBYTES=y
-CONFIG_BAT0_ACCESS_RW=y
-CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_USER_MODE_VALID=y
-CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT1=y
-CONFIG_BAT1_NAME="IMMR"
-CONFIG_BAT1_BASE=0xE0000000
-CONFIG_BAT1_LENGTH_4_MBYTES=y
-CONFIG_BAT1_ACCESS_RW=y
-CONFIG_BAT1_ICACHE_INHIBITED=y
-CONFIG_BAT1_ICACHE_GUARDED=y
-CONFIG_BAT1_DCACHE_INHIBITED=y
-CONFIG_BAT1_DCACHE_GUARDED=y
-CONFIG_BAT1_USER_MODE_VALID=y
-CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT2=y
-CONFIG_BAT2_NAME="BCSR"
-CONFIG_BAT2_BASE=0xF8000000
-CONFIG_BAT2_ACCESS_RW=y
-CONFIG_BAT2_ICACHE_INHIBITED=y
-CONFIG_BAT2_ICACHE_GUARDED=y
-CONFIG_BAT2_DCACHE_INHIBITED=y
-CONFIG_BAT2_DCACHE_GUARDED=y
-CONFIG_BAT2_USER_MODE_VALID=y
-CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT3=y
-CONFIG_BAT3_NAME="FLASH"
-CONFIG_BAT3_BASE=0xFE000000
-CONFIG_BAT3_LENGTH_32_MBYTES=y
-CONFIG_BAT3_ACCESS_RW=y
-CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT3_DCACHE_INHIBITED=y
-CONFIG_BAT3_DCACHE_GUARDED=y
-CONFIG_BAT3_USER_MODE_VALID=y
-CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT5=y
-CONFIG_BAT5_NAME="STACK_IN_DCACHE"
-CONFIG_BAT5_BASE=0xE6000000
-CONFIG_BAT5_ACCESS_RW=y
-CONFIG_BAT5_USER_MODE_VALID=y
-CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
-CONFIG_LBLAW0=y
-CONFIG_LBLAW0_BASE=0xFE000000
-CONFIG_LBLAW0_NAME="FLASH"
-CONFIG_LBLAW0_LENGTH_32_MBYTES=y
-CONFIG_LBLAW1=y
-CONFIG_LBLAW1_BASE=0xF8000000
-CONFIG_LBLAW1_NAME="BCSR"
-CONFIG_LBLAW1_LENGTH_32_KBYTES=y
-CONFIG_LBLAW3=y
-CONFIG_LBLAW3_BASE=0xF8008000
-CONFIG_LBLAW3_NAME="PIB"
-CONFIG_LBLAW3_LENGTH_64_KBYTES=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_16_MBYTES=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="BCSR"
-CONFIG_BR1_OR1_BASE=0xF8000000
-CONFIG_OR1_XAM_SET=y
-CONFIG_OR1_SCY_15=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_XACS_EXTENDED=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_EHTR_8_CYCLE=y
-CONFIG_OR1_EAD_EXTRA=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="PIB1"
-CONFIG_BR2_OR2_BASE=0xF8008000
-CONFIG_OR2_XAM_SET=y
-CONFIG_OR2_SCY_15=y
-CONFIG_OR2_CSNT_EARLIER=y
-CONFIG_OR2_XACS_EXTENDED=y
-CONFIG_OR2_TRLX_RELAXED=y
-CONFIG_OR2_EHTR_8_CYCLE=y
-CONFIG_OR2_EAD_EXTRA=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="PIB2"
-CONFIG_BR3_OR3_BASE=0xF8010000
-CONFIG_OR3_XAM_SET=y
-CONFIG_OR3_SCY_15=y
-CONFIG_OR3_CSNT_EARLIER=y
-CONFIG_OR3_XACS_EXTENDED=y
-CONFIG_OR3_TRLX_RELAXED=y
-CONFIG_OR3_EHTR_8_CYCLE=y
-CONFIG_OR3_EAD_EXTRA=y
-CONFIG_HID0_FINAL_EMCP=y
-CONFIG_HID0_FINAL_ICE=y
-CONFIG_HID2_HBE=y
-CONFIG_LCRR_CLKDIV_2=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1"
-CONFIG_BOOTDELAY=6
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_PING=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_ADDR=0xFE080000
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-# CONFIG_PCI is not set
-CONFIG_QE=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFE000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_CLK_FREQ=66000000
-CONFIG_MPC83xx=y
-CONFIG_HIGH_BATS=y
-CONFIG_TARGET_MPC832XEMDS=y
-CONFIG_CORE_PLL_RATIO_2_1=y
-CONFIG_QUICC_MULT_FACTOR_3=y
-CONFIG_PCI_HOST_MODE_ENABLE=y
-CONFIG_PCI_INT_ARBITER1_ENABLE=y
-CONFIG_BOOT_MEMORY_SPACE_LOW=y
-CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
-CONFIG_BAT0=y
-CONFIG_BAT0_NAME="SDRAM"
-CONFIG_BAT0_BASE=0x00000000
-CONFIG_BAT0_LENGTH_256_MBYTES=y
-CONFIG_BAT0_ACCESS_RW=y
-CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_USER_MODE_VALID=y
-CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT1=y
-CONFIG_BAT1_NAME="IMMR"
-CONFIG_BAT1_BASE=0xE0000000
-CONFIG_BAT1_LENGTH_4_MBYTES=y
-CONFIG_BAT1_ACCESS_RW=y
-CONFIG_BAT1_ICACHE_INHIBITED=y
-CONFIG_BAT1_ICACHE_GUARDED=y
-CONFIG_BAT1_DCACHE_INHIBITED=y
-CONFIG_BAT1_DCACHE_GUARDED=y
-CONFIG_BAT1_USER_MODE_VALID=y
-CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT2=y
-CONFIG_BAT2_NAME="BCSR"
-CONFIG_BAT2_BASE=0xF8000000
-CONFIG_BAT2_ACCESS_RW=y
-CONFIG_BAT2_ICACHE_INHIBITED=y
-CONFIG_BAT2_ICACHE_GUARDED=y
-CONFIG_BAT2_DCACHE_INHIBITED=y
-CONFIG_BAT2_DCACHE_GUARDED=y
-CONFIG_BAT2_USER_MODE_VALID=y
-CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT3=y
-CONFIG_BAT3_NAME="FLASH"
-CONFIG_BAT3_BASE=0xFE000000
-CONFIG_BAT3_LENGTH_32_MBYTES=y
-CONFIG_BAT3_ACCESS_RW=y
-CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT3_DCACHE_INHIBITED=y
-CONFIG_BAT3_DCACHE_GUARDED=y
-CONFIG_BAT3_USER_MODE_VALID=y
-CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT5=y
-CONFIG_BAT5_NAME="STACK_IN_DCACHE"
-CONFIG_BAT5_BASE=0xE6000000
-CONFIG_BAT5_ACCESS_RW=y
-CONFIG_BAT5_USER_MODE_VALID=y
-CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT6=y
-CONFIG_BAT6_NAME="PCI_MEM_PHYS"
-CONFIG_BAT6_BASE=0x80000000
-CONFIG_BAT6_LENGTH_256_MBYTES=y
-CONFIG_BAT6_ACCESS_RW=y
-CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT6_USER_MODE_VALID=y
-CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT7=y
-CONFIG_BAT7_NAME="PCI1_MMIO_PHYS"
-CONFIG_BAT7_BASE=0x90000000
-CONFIG_BAT7_LENGTH_256_MBYTES=y
-CONFIG_BAT7_ACCESS_RW=y
-CONFIG_BAT7_ICACHE_INHIBITED=y
-CONFIG_BAT7_ICACHE_GUARDED=y
-CONFIG_BAT7_DCACHE_INHIBITED=y
-CONFIG_BAT7_DCACHE_GUARDED=y
-CONFIG_BAT7_USER_MODE_VALID=y
-CONFIG_BAT7_SUPERVISOR_MODE_VALID=y
-CONFIG_LBLAW0=y
-CONFIG_LBLAW0_BASE=0xFE000000
-CONFIG_LBLAW0_NAME="FLASH"
-CONFIG_LBLAW0_LENGTH_32_MBYTES=y
-CONFIG_LBLAW1=y
-CONFIG_LBLAW1_BASE=0xF8000000
-CONFIG_LBLAW1_NAME="BCSR"
-CONFIG_LBLAW1_LENGTH_32_KBYTES=y
-CONFIG_LBLAW3=y
-CONFIG_LBLAW3_BASE=0xF8008000
-CONFIG_LBLAW3_NAME="PIB"
-CONFIG_LBLAW3_LENGTH_64_KBYTES=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_16_MBYTES=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="BCSR"
-CONFIG_BR1_OR1_BASE=0xF8000000
-CONFIG_OR1_XAM_SET=y
-CONFIG_OR1_SCY_15=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_XACS_EXTENDED=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_EHTR_8_CYCLE=y
-CONFIG_OR1_EAD_EXTRA=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="PIB1"
-CONFIG_BR2_OR2_BASE=0xF8008000
-CONFIG_OR2_XAM_SET=y
-CONFIG_OR2_SCY_15=y
-CONFIG_OR2_CSNT_EARLIER=y
-CONFIG_OR2_XACS_EXTENDED=y
-CONFIG_OR2_TRLX_RELAXED=y
-CONFIG_OR2_EHTR_8_CYCLE=y
-CONFIG_OR2_EAD_EXTRA=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="PIB2"
-CONFIG_BR3_OR3_BASE=0xF8010000
-CONFIG_OR3_XAM_SET=y
-CONFIG_OR3_SCY_15=y
-CONFIG_OR3_CSNT_EARLIER=y
-CONFIG_OR3_XACS_EXTENDED=y
-CONFIG_OR3_TRLX_RELAXED=y
-CONFIG_OR3_EHTR_8_CYCLE=y
-CONFIG_OR3_EAD_EXTRA=y
-CONFIG_HID0_FINAL_EMCP=y
-CONFIG_HID0_FINAL_ICE=y
-CONFIG_HID2_HBE=y
-CONFIG_LCRR_CLKDIV_2=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PCI_33M,PQ_MDS_PIB=1"
-CONFIG_BOOTDELAY=6
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_PING=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_ADDR=0xFE080000
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_QE=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFE000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_CLK_FREQ=66000000
-CONFIG_MPC83xx=y
-CONFIG_HIGH_BATS=y
-CONFIG_TARGET_MPC832XEMDS=y
-CONFIG_CORE_PLL_RATIO_2_1=y
-CONFIG_QUICC_MULT_FACTOR_3=y
-CONFIG_PCI_HOST_MODE_ENABLE=y
-CONFIG_PCI_INT_ARBITER1_ENABLE=y
-CONFIG_BOOT_MEMORY_SPACE_LOW=y
-CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
-CONFIG_BAT0=y
-CONFIG_BAT0_NAME="SDRAM"
-CONFIG_BAT0_BASE=0x00000000
-CONFIG_BAT0_LENGTH_256_MBYTES=y
-CONFIG_BAT0_ACCESS_RW=y
-CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_USER_MODE_VALID=y
-CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT1=y
-CONFIG_BAT1_NAME="IMMR"
-CONFIG_BAT1_BASE=0xE0000000
-CONFIG_BAT1_LENGTH_4_MBYTES=y
-CONFIG_BAT1_ACCESS_RW=y
-CONFIG_BAT1_ICACHE_INHIBITED=y
-CONFIG_BAT1_ICACHE_GUARDED=y
-CONFIG_BAT1_DCACHE_INHIBITED=y
-CONFIG_BAT1_DCACHE_GUARDED=y
-CONFIG_BAT1_USER_MODE_VALID=y
-CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT2=y
-CONFIG_BAT2_NAME="BCSR"
-CONFIG_BAT2_BASE=0xF8000000
-CONFIG_BAT2_ACCESS_RW=y
-CONFIG_BAT2_ICACHE_INHIBITED=y
-CONFIG_BAT2_ICACHE_GUARDED=y
-CONFIG_BAT2_DCACHE_INHIBITED=y
-CONFIG_BAT2_DCACHE_GUARDED=y
-CONFIG_BAT2_USER_MODE_VALID=y
-CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT3=y
-CONFIG_BAT3_NAME="FLASH"
-CONFIG_BAT3_BASE=0xFE000000
-CONFIG_BAT3_LENGTH_32_MBYTES=y
-CONFIG_BAT3_ACCESS_RW=y
-CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT3_DCACHE_INHIBITED=y
-CONFIG_BAT3_DCACHE_GUARDED=y
-CONFIG_BAT3_USER_MODE_VALID=y
-CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT5=y
-CONFIG_BAT5_NAME="STACK_IN_DCACHE"
-CONFIG_BAT5_BASE=0xE6000000
-CONFIG_BAT5_ACCESS_RW=y
-CONFIG_BAT5_USER_MODE_VALID=y
-CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT6=y
-CONFIG_BAT6_NAME="PCI_MEM_PHYS"
-CONFIG_BAT6_BASE=0x80000000
-CONFIG_BAT6_LENGTH_256_MBYTES=y
-CONFIG_BAT6_ACCESS_RW=y
-CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT6_USER_MODE_VALID=y
-CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT7=y
-CONFIG_BAT7_NAME="PCI1_MMIO_PHYS"
-CONFIG_BAT7_BASE=0x90000000
-CONFIG_BAT7_LENGTH_256_MBYTES=y
-CONFIG_BAT7_ACCESS_RW=y
-CONFIG_BAT7_ICACHE_INHIBITED=y
-CONFIG_BAT7_ICACHE_GUARDED=y
-CONFIG_BAT7_DCACHE_INHIBITED=y
-CONFIG_BAT7_DCACHE_GUARDED=y
-CONFIG_BAT7_USER_MODE_VALID=y
-CONFIG_BAT7_SUPERVISOR_MODE_VALID=y
-CONFIG_LBLAW0=y
-CONFIG_LBLAW0_BASE=0xFE000000
-CONFIG_LBLAW0_NAME="FLASH"
-CONFIG_LBLAW0_LENGTH_32_MBYTES=y
-CONFIG_LBLAW1=y
-CONFIG_LBLAW1_BASE=0xF8000000
-CONFIG_LBLAW1_NAME="BCSR"
-CONFIG_LBLAW1_LENGTH_32_KBYTES=y
-CONFIG_LBLAW3=y
-CONFIG_LBLAW3_BASE=0xF8008000
-CONFIG_LBLAW3_NAME="PIB"
-CONFIG_LBLAW3_LENGTH_64_KBYTES=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_16_MBYTES=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="BCSR"
-CONFIG_BR1_OR1_BASE=0xF8000000
-CONFIG_OR1_XAM_SET=y
-CONFIG_OR1_SCY_15=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_XACS_EXTENDED=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_EHTR_8_CYCLE=y
-CONFIG_OR1_EAD_EXTRA=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="PIB1"
-CONFIG_BR2_OR2_BASE=0xF8008000
-CONFIG_OR2_XAM_SET=y
-CONFIG_OR2_SCY_15=y
-CONFIG_OR2_CSNT_EARLIER=y
-CONFIG_OR2_XACS_EXTENDED=y
-CONFIG_OR2_TRLX_RELAXED=y
-CONFIG_OR2_EHTR_8_CYCLE=y
-CONFIG_OR2_EAD_EXTRA=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="PIB2"
-CONFIG_BR3_OR3_BASE=0xF8010000
-CONFIG_OR3_XAM_SET=y
-CONFIG_OR3_SCY_15=y
-CONFIG_OR3_CSNT_EARLIER=y
-CONFIG_OR3_XACS_EXTENDED=y
-CONFIG_OR3_TRLX_RELAXED=y
-CONFIG_OR3_EHTR_8_CYCLE=y
-CONFIG_OR3_EAD_EXTRA=y
-CONFIG_HID0_FINAL_EMCP=y
-CONFIG_HID0_FINAL_ICE=y
-CONFIG_HID2_HBE=y
-CONFIG_LCRR_CLKDIV_2=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PCI_66M,PQ_MDS_PIB=1"
-CONFIG_BOOTDELAY=6
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_PING=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_ADDR=0xFE080000
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_QE=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFE000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_CLK_FREQ=66000000
-CONFIG_MPC83xx=y
-CONFIG_HIGH_BATS=y
-CONFIG_TARGET_MPC832XEMDS=y
-CONFIG_CORE_PLL_RATIO_2_1=y
-CONFIG_QUICC_MULT_FACTOR_3=y
-CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
-CONFIG_BAT0=y
-CONFIG_BAT0_NAME="SDRAM"
-CONFIG_BAT0_BASE=0x00000000
-CONFIG_BAT0_LENGTH_256_MBYTES=y
-CONFIG_BAT0_ACCESS_RW=y
-CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_USER_MODE_VALID=y
-CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT1=y
-CONFIG_BAT1_NAME="IMMR"
-CONFIG_BAT1_BASE=0xE0000000
-CONFIG_BAT1_LENGTH_4_MBYTES=y
-CONFIG_BAT1_ACCESS_RW=y
-CONFIG_BAT1_ICACHE_INHIBITED=y
-CONFIG_BAT1_ICACHE_GUARDED=y
-CONFIG_BAT1_DCACHE_INHIBITED=y
-CONFIG_BAT1_DCACHE_GUARDED=y
-CONFIG_BAT1_USER_MODE_VALID=y
-CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT2=y
-CONFIG_BAT2_NAME="BCSR"
-CONFIG_BAT2_BASE=0xF8000000
-CONFIG_BAT2_ACCESS_RW=y
-CONFIG_BAT2_ICACHE_INHIBITED=y
-CONFIG_BAT2_ICACHE_GUARDED=y
-CONFIG_BAT2_DCACHE_INHIBITED=y
-CONFIG_BAT2_DCACHE_GUARDED=y
-CONFIG_BAT2_USER_MODE_VALID=y
-CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT3=y
-CONFIG_BAT3_NAME="FLASH"
-CONFIG_BAT3_BASE=0xFE000000
-CONFIG_BAT3_LENGTH_32_MBYTES=y
-CONFIG_BAT3_ACCESS_RW=y
-CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT3_DCACHE_INHIBITED=y
-CONFIG_BAT3_DCACHE_GUARDED=y
-CONFIG_BAT3_USER_MODE_VALID=y
-CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT5=y
-CONFIG_BAT5_NAME="STACK_IN_DCACHE"
-CONFIG_BAT5_BASE=0xE6000000
-CONFIG_BAT5_ACCESS_RW=y
-CONFIG_BAT5_USER_MODE_VALID=y
-CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT6=y
-CONFIG_BAT6_NAME="PCI_MEM_PHYS"
-CONFIG_BAT6_BASE=0x80000000
-CONFIG_BAT6_LENGTH_256_MBYTES=y
-CONFIG_BAT6_ACCESS_RW=y
-CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT6_USER_MODE_VALID=y
-CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT7=y
-CONFIG_BAT7_NAME="PCI1_MMIO_PHYS"
-CONFIG_BAT7_BASE=0x90000000
-CONFIG_BAT7_LENGTH_256_MBYTES=y
-CONFIG_BAT7_ACCESS_RW=y
-CONFIG_BAT7_ICACHE_INHIBITED=y
-CONFIG_BAT7_ICACHE_GUARDED=y
-CONFIG_BAT7_DCACHE_INHIBITED=y
-CONFIG_BAT7_DCACHE_GUARDED=y
-CONFIG_BAT7_USER_MODE_VALID=y
-CONFIG_BAT7_SUPERVISOR_MODE_VALID=y
-CONFIG_LBLAW0=y
-CONFIG_LBLAW0_BASE=0xFE000000
-CONFIG_LBLAW0_NAME="FLASH"
-CONFIG_LBLAW0_LENGTH_32_MBYTES=y
-CONFIG_LBLAW1=y
-CONFIG_LBLAW1_BASE=0xF8000000
-CONFIG_LBLAW1_NAME="BCSR"
-CONFIG_LBLAW1_LENGTH_32_KBYTES=y
-CONFIG_LBLAW3=y
-CONFIG_LBLAW3_BASE=0xF8008000
-CONFIG_LBLAW3_NAME="PIB"
-CONFIG_LBLAW3_LENGTH_64_KBYTES=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_16_MBYTES=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="BCSR"
-CONFIG_BR1_OR1_BASE=0xF8000000
-CONFIG_OR1_XAM_SET=y
-CONFIG_OR1_SCY_15=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_XACS_EXTENDED=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_EHTR_8_CYCLE=y
-CONFIG_OR1_EAD_EXTRA=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="PIB1"
-CONFIG_BR2_OR2_BASE=0xF8008000
-CONFIG_OR2_XAM_SET=y
-CONFIG_OR2_SCY_15=y
-CONFIG_OR2_CSNT_EARLIER=y
-CONFIG_OR2_XACS_EXTENDED=y
-CONFIG_OR2_TRLX_RELAXED=y
-CONFIG_OR2_EHTR_8_CYCLE=y
-CONFIG_OR2_EAD_EXTRA=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="PIB2"
-CONFIG_BR3_OR3_BASE=0xF8010000
-CONFIG_OR3_XAM_SET=y
-CONFIG_OR3_SCY_15=y
-CONFIG_OR3_CSNT_EARLIER=y
-CONFIG_OR3_XACS_EXTENDED=y
-CONFIG_OR3_TRLX_RELAXED=y
-CONFIG_OR3_EHTR_8_CYCLE=y
-CONFIG_OR3_EAD_EXTRA=y
-CONFIG_HID0_FINAL_EMCP=y
-CONFIG_HID0_FINAL_ICE=y
-CONFIG_HID2_HBE=y
-CONFIG_LCRR_CLKDIV_2=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE"
-CONFIG_BOOTDELAY=6
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_PING=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_ADDR=0xFE080000
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_QE=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFE000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_CLK_FREQ=66000000
-CONFIG_MPC83xx=y
-CONFIG_HIGH_BATS=y
-CONFIG_TARGET_MPC832XEMDS=y
-CONFIG_CORE_PLL_RATIO_2_1=y
-CONFIG_QUICC_MULT_FACTOR_3=y
-CONFIG_PCI_HOST_MODE_ENABLE=y
-CONFIG_PCI_INT_ARBITER1_ENABLE=y
-CONFIG_BOOT_MEMORY_SPACE_LOW=y
-CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
-CONFIG_BAT0=y
-CONFIG_BAT0_NAME="SDRAM"
-CONFIG_BAT0_BASE=0x00000000
-CONFIG_BAT0_LENGTH_256_MBYTES=y
-CONFIG_BAT0_ACCESS_RW=y
-CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_USER_MODE_VALID=y
-CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT1=y
-CONFIG_BAT1_NAME="IMMR"
-CONFIG_BAT1_BASE=0xE0000000
-CONFIG_BAT1_LENGTH_4_MBYTES=y
-CONFIG_BAT1_ACCESS_RW=y
-CONFIG_BAT1_ICACHE_INHIBITED=y
-CONFIG_BAT1_ICACHE_GUARDED=y
-CONFIG_BAT1_DCACHE_INHIBITED=y
-CONFIG_BAT1_DCACHE_GUARDED=y
-CONFIG_BAT1_USER_MODE_VALID=y
-CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT2=y
-CONFIG_BAT2_NAME="BCSR"
-CONFIG_BAT2_BASE=0xF8000000
-CONFIG_BAT2_ACCESS_RW=y
-CONFIG_BAT2_ICACHE_INHIBITED=y
-CONFIG_BAT2_ICACHE_GUARDED=y
-CONFIG_BAT2_DCACHE_INHIBITED=y
-CONFIG_BAT2_DCACHE_GUARDED=y
-CONFIG_BAT2_USER_MODE_VALID=y
-CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT3=y
-CONFIG_BAT3_NAME="FLASH"
-CONFIG_BAT3_BASE=0xFE000000
-CONFIG_BAT3_LENGTH_32_MBYTES=y
-CONFIG_BAT3_ACCESS_RW=y
-CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT3_DCACHE_INHIBITED=y
-CONFIG_BAT3_DCACHE_GUARDED=y
-CONFIG_BAT3_USER_MODE_VALID=y
-CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT5=y
-CONFIG_BAT5_NAME="STACK_IN_DCACHE"
-CONFIG_BAT5_BASE=0xE6000000
-CONFIG_BAT5_ACCESS_RW=y
-CONFIG_BAT5_USER_MODE_VALID=y
-CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
-CONFIG_LBLAW0=y
-CONFIG_LBLAW0_BASE=0xFE000000
-CONFIG_LBLAW0_NAME="FLASH"
-CONFIG_LBLAW0_LENGTH_32_MBYTES=y
-CONFIG_LBLAW1=y
-CONFIG_LBLAW1_BASE=0xF8000000
-CONFIG_LBLAW1_NAME="BCSR"
-CONFIG_LBLAW1_LENGTH_32_KBYTES=y
-CONFIG_LBLAW3=y
-CONFIG_LBLAW3_BASE=0xF8008000
-CONFIG_LBLAW3_NAME="PIB"
-CONFIG_LBLAW3_LENGTH_64_KBYTES=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_16_MBYTES=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="BCSR"
-CONFIG_BR1_OR1_BASE=0xF8000000
-CONFIG_OR1_XAM_SET=y
-CONFIG_OR1_SCY_15=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_XACS_EXTENDED=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_EHTR_8_CYCLE=y
-CONFIG_OR1_EAD_EXTRA=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="PIB1"
-CONFIG_BR2_OR2_BASE=0xF8008000
-CONFIG_OR2_XAM_SET=y
-CONFIG_OR2_SCY_15=y
-CONFIG_OR2_CSNT_EARLIER=y
-CONFIG_OR2_XACS_EXTENDED=y
-CONFIG_OR2_TRLX_RELAXED=y
-CONFIG_OR2_EHTR_8_CYCLE=y
-CONFIG_OR2_EAD_EXTRA=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="PIB2"
-CONFIG_BR3_OR3_BASE=0xF8010000
-CONFIG_OR3_XAM_SET=y
-CONFIG_OR3_SCY_15=y
-CONFIG_OR3_CSNT_EARLIER=y
-CONFIG_OR3_XACS_EXTENDED=y
-CONFIG_OR3_TRLX_RELAXED=y
-CONFIG_OR3_EHTR_8_CYCLE=y
-CONFIG_OR3_EAD_EXTRA=y
-CONFIG_HID0_FINAL_EMCP=y
-CONFIG_HID0_FINAL_ICE=y
-CONFIG_HID2_HBE=y
-CONFIG_LCRR_CLKDIV_2=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=6
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_PING=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_ADDR=0xFE080000
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-# CONFIG_PCI is not set
-CONFIG_QE=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300 1 /* E300 family */
-
-/*
- * System IO Config
- */
-#define CONFIG_SYS_SICRL 0x00000000
-
-/*
- * DDR Setup
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */
-
-#undef CONFIG_SPD_EEPROM
-#if defined(CONFIG_SPD_EEPROM)
-/* Determine DDR configuration from I2C interface
- */
-#define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */
-#else
-/* Manually set up DDR parameters
- */
-#define CONFIG_SYS_DDR_SIZE 128 /* MB */
-#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
- | CSCONFIG_AP \
- | CSCONFIG_ODT_WR_CFG \
- | CSCONFIG_ROW_BIT_13 \
- | CSCONFIG_COL_BIT_10)
- /* 0x80840102 */
-#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
- | (0 << TIMING_CFG0_WRT_SHIFT) \
- | (0 << TIMING_CFG0_RRT_SHIFT) \
- | (0 << TIMING_CFG0_WWT_SHIFT) \
- | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
- | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
- | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
- | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
- /* 0x00220802 */
-#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
- | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
- | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
- | (5 << TIMING_CFG1_CASLAT_SHIFT) \
- | (13 << TIMING_CFG1_REFREC_SHIFT) \
- | (3 << TIMING_CFG1_WRREC_SHIFT) \
- | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
- | (2 << TIMING_CFG1_WRTORD_SHIFT))
- /* 0x3935D322 */
-#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
- | (31 << TIMING_CFG2_CPO_SHIFT) \
- | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
- | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
- | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
- | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
- | (10 << TIMING_CFG2_FOUR_ACT_SHIFT))
- /* 0x0F9048CA */
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
- /* 0x02000000 */
-#define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
- | (0x0232 << SDRAM_MODE_SD_SHIFT))
- /* 0x44400232 */
-#define CONFIG_SYS_DDR_MODE2 0x8000c000
-#define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
- | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
- /* 0x03200064 */
-#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
-#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
- | SDRAM_CFG_SDRAM_TYPE_DDR2 \
- | SDRAM_CFG_32_BE)
- /* 0x43080000 */
-#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
-#endif
-
-/*
- * Memory test
- */
-#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
-
-/*
- * The reserved memory
- */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#else
-#undef CONFIG_SYS_RAMBOOT
-#endif
-
-/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
-
-/*
- * Initial RAM Base Address Setup
- */
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM addr */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-/*
- * FLASH on the Local Bus
- */
-#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
-#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
-
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-
-/*
- * BCSR on the Local Bus
- */
-#define CONFIG_SYS_BCSR 0xF8000000
- /* Access window base at BCSR base */
-
-
-/*
- * Windows to access PIB via local bus
- */
- /* PIB window base 0xF8008000 */
-#define CONFIG_SYS_PIB_BASE 0xF8008000
-#define CONFIG_SYS_PIB_WINDOW_SIZE (32 * 1024)
-
-/*
- * CS2 on Local Bus, to PIB
- */
-
-
-/*
- * CS3 on Local Bus, to PIB
- */
-
-
-/*
- * Serial Port
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
-
-/*
- * Config on-board RTC
- */
-#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
-#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
-#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
-#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000
-#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
-
-#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
-#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
-
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-
-#define CONFIG_83XX_PCI_STREAMING
-
-#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
-
-#endif /* CONFIG_PCI */
-
-/*
- * QE UEC ethernet configuration
- */
-#define CONFIG_UEC_ETH
-#define CONFIG_ETHPRIME "UEC0"
-
-#define CONFIG_UEC_ETH1 /* ETH3 */
-
-#ifdef CONFIG_UEC_ETH1
-#define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */
-#define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
-#define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
-#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
-#define CONFIG_SYS_UEC1_PHY_ADDR 3
-#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
-#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
-#endif
-
-#define CONFIG_UEC_ETH2 /* ETH4 */
-
-#ifdef CONFIG_UEC_ETH2
-#define CONFIG_SYS_UEC2_UCC_NUM 3 /* UCC4 */
-#define CONFIG_SYS_UEC2_RX_CLK QE_CLK7
-#define CONFIG_SYS_UEC2_TX_CLK QE_CLK8
-#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
-#define CONFIG_SYS_UEC2_PHY_ADDR 4
-#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
-#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
-#endif
-
-/*
- * Environment
- */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
- /* Initial Memory map for Linux */
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
-#endif
-
-#if defined(CONFIG_UEC_ETH)
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#endif
-
-#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=1000000\0" \
- "ramdiskfile=ramfs.83xx\0" \
- "fdtaddr=780000\0" \
- "fdtfile=mpc832x_mds.dtb\0" \
- ""
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
- "$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
-
-#endif /* __CONFIG_H */
projects / u-boot.git / commitdiff