From b9d1671829b17f78c47f2d0d42a7f59767cdd84b Mon Sep 17 00:00:00 2001
From: Ley Foon Tan <ley.foon.tan@intel.com>
Date: Mon, 20 Apr 2020 16:17:27 +0800
Subject: [PATCH] arm: socfpga: stratix10: Fix incorrect
 CLKMGR_S10_PERPLL_BYPASS offset

Offset value for CLKMGR_S10_PERPLL_BYPASS should be 0xb0, fix it.

Reported-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
---
 arch/arm/mach-socfpga/include/mach/clock_manager_s10.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
index e710aa2f94..9d2b3babab 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
@@ -85,7 +85,7 @@ void cm_basic_init(const struct cm_config * const cfg);
 #define CLKMGR_S10_MAINPLL_VCOCALIB			0x8c
 /* Periphpll group */
 #define CLKMGR_S10_PERPLL_EN				0xa4
-#define CLKMGR_S10_PERPLL_BYPASS			0xac
+#define CLKMGR_S10_PERPLL_BYPASS			0xb0
 #define CLKMGR_S10_PERPLL_CNTR2CLK			0xbc
 #define CLKMGR_S10_PERPLL_CNTR3CLK			0xc0
 #define CLKMGR_S10_PERPLL_CNTR4CLK			0xc4
-- 
2.39.5